JAJU446A December   2017  – January 2022

 

  1.   概要
  2.   Resources
  3.   特長
  4.   アプリケーション
  5.   5
  6. 1 System Description
    1. 1.1 Key System Specifications
  7. 2 System Overview
    1. 2.1 Block Diagram
    2. 2.2 System-Level Description
    3. 2.3 Highlighted Products
      1. 2.3.1 Analog Signal Chain
        1. 2.3.1.1 LMH5401
        2. 2.3.1.2 LHM6401
        3. 2.3.1.3 BUF802
      2. 2.3.2 Clock
        1. 2.3.2.1 LMK61E2
        2. 2.3.2.2 LMK04828
        3. 2.3.2.3 LMX2594
      3. 2.3.3 Power
        1. 2.3.3.1 TPS82130
        2. 2.3.3.2 TPS7A84
    4. 2.4 System Design Theory
      1. 2.4.1 High-Speed, Low-Phase Noise Clock Generation
      2. 2.4.2 Channel-to-Channel Skew
      3. 2.4.3 Deterministic Latency
        1. 2.4.3.1 Importance of Deterministic Latency
      4. 2.4.4 Analog Front End
      5. 2.4.5 Multichannel System Power Requirement
      6. 2.4.6 Hardware Programming
  8. 3 Circuit Design
    1. 3.1 Analog Input Front End
      1. 3.1.1 High-Input Impedance Buffer Implementation Using the BUF802
    2. 3.2 High-Speed Multichannel Clocking
    3. 3.3 Power Supply Section
      1. 3.3.1 DC-DC
        1. 3.3.1.1 How to Set 2.1-V Output Voltage
      2. 3.3.2 LDOs
  9. 4 Host Interface
  10. 5 Hardware Functional Block
  11. 6 Getting Started Application GUI
  12. 7 Testing and Results
    1. 7.1 Test Setup and Test Plan
    2.     44
    3. 7.2 SNR Measurement Test
    4. 7.3 Channel-to-Channel Skew Measurement Test
    5. 7.4 Performance Test Result
    6. 7.5 Multichannel Skew Measurement
    7. 7.6 49
  13. 8 Design Files
    1. 8.1 Schematics
    2. 8.2 Bill of Materials
    3. 8.3 Altium Project
    4. 8.4 Gerber Files
    5. 8.5 Assembly Drawings
  14. 9 Software Files
  15. 10Related Documentation
    1. 10.1 Trademarks
  16. 11About the Authors
    1. 11.1 Acknowledgment
  17. 12Revision History

7.5 Multichannel Skew Measurement

Table 7-2 lists the measured time skew between two channels (CH1 and CH3) of the TIDA-01022 design at room temperature with a 997-MHz input signal and at a sampling frequency of 2700 MHz. Evaluate this skew by calculating the phase difference between signals captured from each ADC. This measurement for both signal chain inputs and the measured time skew was less than 5 ps. Table 7-2 shows the skew measured between two channels for both the transformer input and FDA input path. Figure 7-10 shows the corresponding skew measurement data plot and Figure 7-11 shows the sampled signals in the time domain plot.

Table 7-2 TIDA-01022 CH1 to CH3 Skew Measurement
SAMPLE CYCLETRANSFORMER COUPLING INPUTFDA INPUT (LMH5401+6401)
10.243 ps0.623 ps
20.156 ps0.695 ps
30.575 ps0.749 ps
40.511 ps0.265 ps
50.824 ps0.484 ps
60.669 ps0.339 ps
70.83 ps1.04 ps
80.623 ps0.795 ps
90.72 ps0.712 ps
100.629 ps0.835 ps
GUID-2DA74307-6B46-4514-B3F8-6D9FD3FE4F62-low.gifFigure 7-10 Channel-to-Channel Measurement Plot
GUID-F84913FE-8419-49C0-83A0-1B85914CD0DE-low.gifFigure 7-11 Channel-to-Channel Skew Measurement GUI

Figure 7-12 shows that the time domain measured plot of the ADC1 and ADC2 corresponds to CH1 and CH3 of the TIDA-01022 design.

GUID-0A7D1BC3-C81C-4DAE-83D5-AE17853607E3-low.gifFigure 7-12 Sampled Signal at 997 MHz