SLAU966 February   2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of NXP M0 MCUs to MSPM0
  5. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 MCUXpresso IDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 MCUXpresso Code Configuration Tool vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Memory Banks
        2. 3.2.2.2 Flash Memory Regions
        3. 3.2.2.3 NONMAIN Memory
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Power Modes
      3. 3.5.3 Entering Lower-Power Modes
    6. 3.6 Interrupt and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
      2. 3.6.2 Event Handler and Extended Interrupt and Event Controller (EXTI)
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6References

3.6.1 Interrupts and Exceptions

The MSPM0 and NXP MCUs both register and map interrupt and exception vectors depending on the device's available peripherals. A summary and comparison of the interrupt vectors for each family of devices is included in Table 3-9. A lower value of priority for an interrupt or exception is given higher precedence over interrupts with a higher priority value. For some of these vectors the priority is user-selectable, and for others it is fixed.

For both MSPM0 and NXP MCUs, exceptions such as NMI, reset, and hard fault handlers are given negative priority values to indicate that they always have the highest precedence over peripheral interrupts. For peripherals with selectable interrupt priorities, up to four programmable priority levels are available on both families of devices.

Table 3-9 Interrupt Comparison
IRQ Number NXP MSPM0
Interrupt/Exception Priority Interrupt/Exception Priority
- Reset Re Fixed: -3
- NMI Handler NMI Handler Fixed: -2
- Hard Fault Handler Hard Fault Handler Fixed: -1
- SVCall Handler SVCall Handler Selectable
- PendSV PendSV Selectable
- SysTick SysTick Selectable
0 DMA0: KM35x Selectable INT_GROUP0-6 [WWDT0, DEBUGSS, FLASHCTL, WUC FSUBx, and SYSCTL]: M0G Selectable
INT_GROUP0,2-6 [WWDT0, DEBUGSS, FLASHCTL, WUC FSUBx, and SYSCTL]: M0L
INT_GROUP0-6 [WWDT0, DEBUGSS, FLASHCTL, and SYSCTL]: M0C
1 DMA1: KM35x Selectable INT_GROUP0-5 [GPIO0, GPIO1, COMP0,COMP1,COMP2,TRNG]: M0G Selectable
INT_GROUP0,2 [GPIO0, COMP0]: M0L
GPIO0: M0C
2 DMA2: KM35x Selectable TIMG8:M0G, M0C Selectable
TIMG1: M0L
3 DM3: KM35x Selectable UART3:M0G Selectable
4 SPI0/SPI1/SPI2: KM35x Selectable ADC0: M0G Selectable
ADC: M0L, M0C
5 FTMRE: KEA128x Selectable ADC1: M0G Selectable
PDB0:KM35x
6 PMC: KE128x/KM35x Selectable CANFD0: M0G Selectable
7 TMR0: KM35x Selectable DAC0: M0G Selectable
EXT IRQ: KE128x
8 TMR1: KM35x Selectable Reserved Selectable
I2C0: KEA128x
9 TMR2: KM35x Selectable SPI0: M0G, M0L, M0C Selectable
I2C1: KEA128x
10 TMR3: KM35x Selectable SPI1: M0G, M0L, M0C Selectable
SPI0: KEA128x
11 PIT0/PIT1: KM35x Selectable Reserved Selectable
SPI1: KEA128x
12 LLWU: KM35x Selectable Reserved Selectable
UART0: KEA128x
13 FLASH: KM35x Selectable UART1: M0G, M0L Selectable
UART1: KEA128x
14 ACMP0/ACMP1/ACMP2: KM35x Selectable UART2 Selectable
UART2: KEA128x
15 SLCD: KM35x Selectable UART0: M0G, M0L, M0C Selectable
ADC0: KEA128x
16 ADC: KM35x Selectable TIMG0: M0G, M0L Selectable
ACMP0: KEA128x TIMG14: M0C
17 PTx: KM35x Selectable TIMG6: M0G Selectable
FTM0: KEA128x
18 RNGA: KM35x Selectable TIMA0: M0G Selectable
FTM1: KEA128x TIMG2: M0L
TIMA0: M0C
19 UARTx: KM35x Selectable TIMA1: M0G Selectable
FTM2: KEA128x
20 MMAU: KM35x Selectable TIMG7: M0G Selectable
RTC: KEA128x TIMG4: M0L
21 AFE_CH0: KM35x Selectable TIMG12: M0G Selectable
ACMP1: KEA128x
22 AFE_CH1: KM35x Selectable Reserved Selectable
PIT_CH0: KEA128x
23 AFE_CH2: KM35x Selectable Reserved Selectable
PIT_CH1: KEA128x
24 AFE_CH3: KM35x Selectable I2C0: M0G, M0L, M0C Selectable
KBIO: KEA128x
25 iRTC: KM35x Selectable I2C1: M0G, M0L, M0C Selectable
KBI1: KEA128x
26 I2C0/I2C1: KM35x Selectable Reserved Selectable
Reserved: KEA128x
27 LPUART0: KM35x Selectable Reserved Selectable
ICS: KEA128x
28 MCG: KM35x Selectable AES: M0G Selectable
WDOG: KEA128x
29 WDOG/EWM: KM35x Selectable Reserved Selectable
PWT: KEA128x
30 LPTMR0/LPTRM1: KM35x Selectable RTC: M0G Selectable
MSCAN_RX: KEA128x
31 XBAR: KM35x Selectable DMA : M0G, M0L, M0C Selectable
MSCAN_TX: KEA128x