SLVA469D June   2013  – January 2023 TLV62130 , TLV62130A , TLV62150 , TLV62150A , TPS61175 , TPS61175-Q1 , TPS62130 , TPS62130A , TPS62131 , TPS62132 , TPS62133 , TPS62135 , TPS62136 , TPS62140 , TPS62140A , TPS62141 , TPS62142 , TPS62143 , TPS62150 , TPS62150A , TPS62151 , TPS62152 , TPS62153 , TPS62160 , TPS62161 , TPS62162 , TPS62163 , TPS62170 , TPS62171 , TPS62172 , TPS62173

 

  1.   Using the TPS6215x in an Inverting Buck-Boost Topology
  2.   Trademarks
  3. 1Inverting Buck-Boost Topology
    1. 1.1 Concept
    2. 1.2 Output Current Calculations
    3. 1.3 VIN and VOUT Range
  4. 2Design Considerations
    1. 2.1 Design Precautions
    2. 2.2 Additional Input Capacitor
    3. 2.3 Digital Pin Configurations
      1. 2.3.1 Digital Input Pins (EN, FSW, DEF)
      2. 2.3.2 Power Good Pin
    4. 2.4 Startup Behavior and Switching Node Consideration
  5. 3External Component Selection
    1. 3.1 Inductor Selection
    2. 3.2 Capacitor Selection
  6. 4Typical Performance
  7. 5Conclusion
  8. 6References
  9. 7Revision History

2.3.2 Power Good Pin

These devices have a built-in power good (PG) function to indicate whether the output voltage has reached its appropriate level or not. The PG pin is an open-drain output that requires a pullup resistor. Because VOUT is the IC ground in this configuration, the PG pin is referenced to VOUT instead of ground, which means that the device pulls PG to VOUT when it is low.

This behavior can cause difficulties in reading the state of the PG pin, because in some applications the IC detecting the polarity of the PG pin may not be able to withstand negative voltages. The level shifter circuit shown in Figure 2-7 alleviates any difficulties associated with the offset PG pin voltages by eliminating the negative output signals of the PG pin. If the PG pin functionality is not needed, it may be left floating or connected to VOUT without this circuit. Note that to avoid violating its absolute maximum rating, the PG pin should not be driven more than 7 V above the negative output voltage (IC ground).

GUID-A3DC65BF-65F9-4B20-894C-845D95695F24-low.gifFigure 2-7 PG Pin Level Shifter

Inside these devices, the PG pin is connected to an N-channel MOSFET (Q3). By tying the PG pin to the gate of Q1, when the PG pin is pulled low, Q1 is off and Q2 is on because its VGS sees VCC. SYS_PG is then pulled to ground.

When Q3 turns off, the gate of Q1 is pulled to ground potential turning it on. This pulls the gate of Q2 below ground, turning it off. SYS_PG is then pulled up to the VCC voltage. Note that the VCC voltage must be at an appropriate logic level for the circuitry connected to the SYS_PG net.

This PG pin level shifter sequence is illustrated in Figure 2-8 and Figure 2-9. The PG signal activates the PG pin level shifter circuit, and the GD Node signal represents the shared node between Q1 and Q2. This circuit was tested with a VCC of 1.8 V and dual NFET Si1902DL. The SYS_PG net is the output of the circuit and goes between ground and 1.8 V, and is easily read by a separate device.

GUID-4DAA43FA-7C96-4200-B016-FAC3577F8A9D-low.gifFigure 2-8 PG Pin Level Shifter on Startup
GUID-5B4F17C0-7DC1-4798-B081-C6D77643E3D1-low.gifFigure 2-9 PG Pin Level Shifter on Shutdown