SLVAF10 March   2021 TPS1H000-Q1 , TPS1H100-Q1 , TPS1H200A-Q1 , TPS1HA08-Q1 , TPS1HB08-Q1 , TPS1HB16-Q1 , TPS1HB35-Q1 , TPS1HB50-Q1 , TPS2H000-Q1 , TPS2H160-Q1 , TPS2HB16-Q1 , TPS2HB35-Q1 , TPS2HB50-Q1 , TPS4H000-Q1 , TPS4H160-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Thermals
  4. 3Timing Limitations
    1. 3.1 Background
    2. 3.2 Pulse-Width distortion (PWD)
      1. 3.2.1 Timing Impact of Delay Mismatch
      2. 3.2.2 Power Impact of Delay Mismatch on Resistive Loads
    3. 3.3 Finite Slew Rate
      1. 3.3.1 Timing Impact of Finite Slew Rate and Slew Rate Mismatch
      2. 3.3.2 Impact of Finite Slew Rate on Resistive Load Power
      3. 3.3.3 Impact of Slew Rate on LED Power
  5. 4System-Level Considerations
    1. 4.1 Diagnostics and Protection
      1. 4.1.1 Analog Current Sense
    2. 4.2 Dimming Ratio
    3. 4.3 Side-Stepping Frequency Limitations
  6. 5References

Power Impact of Delay Mismatch on Resistive Loads

The reduction of output pulse-width accuracy has an even greater effect on the accuracy of power delivered to a resistive load since load power is proportional to the square of the current delivered.

LED power analysis taking the example of a resistive load scenario:

Equation 16. GUID-E6246E7E-45FF-4D1E-A7A1-F5C5A379FBC1-low.png
Equation 17. GUID-69E2D378-CEDF-485D-99C6-4416F53F0104-low.png
Equation 18. GUID-7432E4BA-5F67-4B27-8B69-637CFCBF9E2E-low.png
Equation 19. GUID-D5E49CE5-1CA3-4DB6-9956-C76E9D9B44D5-low.png
And
Equation 20. GUID-E01BA97D-88A3-4EE2-A627-90430B2A013B-low.png

Substituting input duty cycle from Equation 47,

Equation 21. GUID-BAF75541-2DB5-4997-B4D5-8EB2873315D0-low.png

We can visualize the worst-case effects of pulse-width distortion on a resistive load scenario with the following conditions:

  • HSS supply voltage: Vvs = 10 V
  • Load resistance: Rload = 10 Ω
  • PWM Duty Cycle: DIN = 50%
  • Pulse-width distortion: td(PWD) = ±50 μs (TPS4H000-Q1 min/max spec)

We can also quantify the variation of actual power dissipation due to compared to ideal.

Equation 22. GUID-C8EE065A-0A96-4A94-92E0-98FE5F197525-low.png

Using the example of TPS4H000-Q1,

  • PWM Duty Cycle: DIN = 50%
  • Pulse-width distortion: td(PWD) = ±50 μs (TPS1H100 min/max spec)

We can see that if we consider a worst-case PWD scenario of TPS4H000-Q1, switching frequency is virtually limited to below 1 kHz again if relatively accurate load power is desired at 50% duty cycle. This figure is even lower if high accuracy is required at low duty cycles.

GUID-9F97C084-4D2F-4656-8E0C-CA2585A809F2-low.png Figure 3-6 Potential Load Power Variation for TPS4H000, Normalized