SLVUBT8B November   2020  – June 2022 LP8764-Q1 , TPS6594-Q1


  1.   Scalable PMIC's GUI User’s Guide
  2.   Trademarks
  3. Introduction
  4. Supported Features
  5. Revisions
  6. Overview
  7. Getting Started
    1. 5.1 Finding the GUI
    2. 5.2 Downloading the Required Software
    3. 5.3 Launching the GUI
    4. 5.4 Connecting to a PMIC
  8. Quick-start Page
    1. 6.1 Device Scan Results
    2. 6.2 Configuration and Monitoring
      1. 6.2.1 System Info
      2. 6.2.2 BUCK
      3. 6.2.3 LDO
      4. 6.2.4 GPIO
      5. 6.2.5 Interrupts
      6. 6.2.6 Miscellaneous Settings
      7. 6.2.7 Advanced
  9. Register Map Page
  10. NVM Configuration Page
    1. 8.1 Creating a Custom Configuration
      1. 8.1.1 Static Configuration
      2. 8.1.2 Pre-Configurable Mission States (PFSM)
        1. Creating a State Diagram
        2. Global Settings
        3. Power Sequence
          1. Power Sequence Resources and Commands
          2. Sub-sequences
          3. Power Sequence Editing Tools
        4. Trigger Settings
        5. Trigger Priority List
        6. PFSM Validation
    2. 8.2 Program
      1. 8.2.1 Program an Existing NVM Configuration
      2. 8.2.2 NVM Configuration Special Use Case: Changing the Communication Interface
      3. 8.2.3 Lock Option During NVM Programming
  11. NVM Validation Page
  12. 10Watchdog Page
  13. 11Additional Resources
  14. 12Appendix A: Troubleshooting
    1. 12.1 Hardware Platform Not Recognized
    2. 12.2 PMIC Device Not Found
    3. 12.3 I2C2 is configured but not connected
  15. 13Appendix B: Advanced Topics
    1. 13.1 Scripting Window
  16. 14Appendix C: Known Limitations
  17. 15Appendix D: Migration Topics
    1. 15.1 Migrating from LP8764-Q1 PG1.0 to PG2.0
    2. 15.2 Update the PFSM to Include the PFSM_START State
    3. 15.3 Update Timing Delays
    4. 15.4 Update Trigger Priority and Settings
  18. 16Revision History

Global Settings

As states are added they will appear in the GLOBAL SETTINGS panel, as shown in Figure 8-14. The names of the states are configurable but the type of state is limited to either a user definition or a Hardware State. Hardware states are already defined within the finite state machine within the PMIC and by definition there is no power sequence associated with transitions to hardware states, with the exception of LP_STANDBY, and no transitions can be defined from Hardware states.

GUID-A94B14E0-8C25-4991-80A0-DE324DD7923B-low.png Figure 8-14 Global Settings

The PFSM will always start from the PFSM_START state. This state includes all of the TRIG_SET definitions as well as the initial TRIG_MASK. By default the TRIG_MASK found in the PFSM_START is defined by the arrows leaving the PFSM_START state in the GUI. No arrows can be defined to the PFSM_START state. From the GLOBAL SETTINGS the user can edit the TRIG_MASK in the PFSM_START state and also add instructions which will be appended to the PFSM_START sequence after the last TRIG_SET instruction.

The PFSM Step Delay setting is also part of the GLOBAL SETTINGS. The PFSM Step Delay setting will determine which time interval the GUI will use to attempt to meet the required delays found throughout the power sequences. The actual delays are a function of the desired delay, instruction being used, as well as the PFSM Step Delay. Instruction delays are limited to either 6 or 8-bit multiples of the step delay. In the event that the GUI cannot reach the desired delay time with the existing step delay, or if the step size is actually larger than the desired delay, then the GUI will generate an error during the PFSM validation. Table 8-2 is provided to exemplify the actual delay versus requested delay times as a function of the PFSM Step Delay.

Note: Choosing a PFSM Step Delay which is a common factor of the majority of the delays needed in power sequencing will optimize the memory usage in the device.
Table 8-2 Examples of Requested and Actual Delay Times
PFSM Step Delay (us) Delay Requested(us) Delay Instruction Actual Delay(1) (us)
25.6 2500 DELAY_IMM (8-bit) 2483.2
REG_WRITE_VCTRL_IMM(6-bit) 2457.6
204.8 40000 DELAY_IMM (8-bit) 39936
REG_WRITE_VCTRL_IMM(6-bit) 39321
409.6 300000 DELAY_IMM (8-bit) 299827
REG_WRITE_VCTRL_IMM(6-bit) 294912