SLVUC05A November 2020 – July 2022 TPS25750
Description | The 'I2Cr' task may be used to cause the PD controller to read from a specified slave address and register offset using a I2C read transaction via the I2Cm_SDA and I2Cm_SCL pins. | ||
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INPUT DATA | Bit | Name | Description |
Byte 3: Number of bytes to read from the slave. | |||
7:0 | NumBytes. | ||
Byte 2: Register offset to use in the I2C read transaction. | |||
7:0 | RegisterOffset. | ||
Byte 1: Slave Address. | |||
7 | Reserved. | ||
6:0 | Slave to use for the transaction. | ||
OUTPUT DATA | Bit | Name | Description |
Bytes 2-65: Data Bytes read from the slave (in order received). | |||
511:0 | Data. | ||
Byte 1: Standard Task Return Code. See also Table 3-1. | |||
Task Completion | The PD controller completes after it has succesfully read the specified number of bytes, or the I2C transaction terminated for some other reason. | ||
Side Effects | This task will cause the PD controller to issue a command on the I2Cm port. It can result in INT_EVENT. I2CMasterNACKed being asserted. | ||
Additional Information | None. |