SNVU590A October   2018  – July 2025 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  6. 3Configuration
    1. 3.1 Configuration Sequence
    2. 3.2 Default OTP Configurations
    3. 3.3 Recommended Order of Configuring Registers Through I2C
      1. 3.3.1 Voltage Settings
      2. 3.3.2 Current Limit and Other Regulator Settings
      3. 3.3.3 GPO Settings
      4. 3.3.4 Clock Sync Functions
      5. 3.3.5 PGOOD Settings
      6. 3.3.6 Interrupt Settings
      7. 3.3.7 Startup and Shutdown Sequence
      8. 3.3.8 Set ENx Pin Control Bits
      9. 3.3.9 Set EN_BUCKx Bits
  7. 4Revision History

3.2 Default OTP Configurations

All LP8756x-Q1 PMIC resource settings are stored in the form of volatile registers. These settings define buck output voltages, GPIO functionality, and power-up and power-down sequences. For a full list of the setting registers, see the device-specific data sheet. A different OTP is needed for each possible phase configuration. Phase configuration is not I2C configurable.

Each device has predefined values stored in OTP which control the default configuration of the device. For the default OTP-programmed values for each device, see the device-specific Technical Reference Manual (TRM ). The tables in this section list the configurability of each bit.

Table 3-1 shows device settings for BUCK0, BUCK1, BUCK2, BUCK3. Maximum allowed slew-rate for BUCKx depends on the output capacitance. For output capacitance boundary conditions, see the device-specific data sheet.

Table 3-1 BUCKx OTP Settings
Description Bit Name Configurable
General settings Buck phase configuration (for example, four single phase denoted as 1+1+1+1, four phase single output denoted as 4 ph). For multiphase configuration master buck defines the output voltage, startup/shutdown times, and so forth. but peak current limits must be set for all bucks. For more information, see the device-specific data sheet. - No
Refer to part number: LP87561x - 4 ph
LP87562x - 3+1
LP87563x - 2+1+1
LP87564x - 1+1+1+1
LP87565x - 2+2
Switching frequency - No
Spread spectrum EN_SPREAD_SPEC Yes
Startup and shutdown delay range, 0...4.8ms / 0... 10ms / 0...15ms / 0...30ms DOUBLE_DELAY, HALF_DELAY Yes
BUCK settings Output voltage BUCKx_VSET Yes
Enable, ENx-pin or I2C register EN_PIN_CTRLx Yes
Control for BUCK0 EN_BUCKx Yes
Force PWM mode or auto mode BUCKx_FPWM Yes
Force multiphase mode or auto mode BUCKx_FPWM_MP Yes
Peak current limit ILIMx Yes
Slew rate SLEW_RATEx Yes
Startup Delay BUCKx_STARTUP_DELAY Yes
Shutdown Delay BUCKx_SHUTDOWN_DELAY Yes

Table 3-2 lists the device settings for GPIOs.

Table 3-2 EN, CLKIN and GPIO Pin Settings
Description Bit Name Configurable
EN1 (GPIO1) pin EN1 (GPIO1) pin pulldown resistor enable or disable EN1_PD Yes
EN2 (GPIO2) pin EN2 (GPIO2) pin pulldown resistor enable or disable EN2_PD Yes
EN3 (GPIO3) pin EN3 (GPIO3) pin pulldown resistor enable or disable EN3_PD Yes
CLKIN pin CLKIN pin pull-down resistor enable or disable CLKIN_PD Yes
Frequency of external clock when connected to CLKIN EXT_CLK_FREQ Yes
Mode for the internal PLL. When PLL disabled, internal RC OSC is used PLL_MODE Yes
EN1 (GPIO) control Enable or GPIO GPIO1_SEL Yes
Input or output in GPIO mode GPIO1_DIR Yes
Output type open drain or push-pull GPIO1_OD Yes
Default state of GPIO output GPIO1_OUT Yes
EN2 (GPIO) control Enable or GPIO GPIO2_SEL Yes
Input or output in GPIO mode GPIO2_DIR Yes
Output type open drain or push-pull GPIO2_OD Yes
Default state of GPIO output GPIO2_OUT Yes
Pin control of GPIO, EN2 or EN3 EN_PIN_CTRL_GPIO2, EN_PIN_SELECT_GPIO2 Yes
Startup Delay GPIO2_ STARTUP_DELAY Yes
Shutdown Delay GPIO2_ SHUTDOWN_DELAY Yes
EN3 (GPIO) control Enable or GPIO GPIO3_SEL Yes
Input or output in GPIO mode GPIO3_DIR Yes
Output type open drain or push-pull GPIO3_OD Yes
Default state of GPIO output GPIO3_OUT Yes
Pin control of GPIO, EN2 or EN3 EN_PIN_CTRL_GPIO3, EN_PIN_SELECT_GPIO3 Yes
Startup Delay GPIO3_ STARTUP_ DELAY Yes
Shutdown Delay GPIO3_ SHUTDOWN_ DELAY Yes

Table 3-3 shows device settings for PGOOD.

Table 3-3 PGOOD OTP Settings
Description Bit Name Configurable
Signals monitored by PGOOD BUCKx output voltage / voltage and current (master bucks) PGx_SEL Yes
PGOOD mode selections PGOOD thresholds for BUCKx (Undervoltage / Window (undervoltage and overvoltage)) PGOOD_WINDOW Yes
PGOOD valid debounce time PGOOD_SET_DELAY Yes
PGOOD signal mode (status / latched until fault source read) EN_PGFLT_STAT Yes
PGOOD output mode (push-pull or open drain) PGOOD_OD Yes
PGOOD polarity (active high / active low) PGOOD_POL Yes

Table 3-4 lists the device settings for thermal warning. For interrupt settings, see Table 3-6.

Table 3-4 Protections OTP Settings
Description Bit Name Configurable
Protections Thermal warning level (125°C or 137°C) TDIE_WARN_LEVEL Yes
Input over-voltage protection - No

Table 3-5 shows device settings for I2C and OTP revision ID values.

Table 3-5 Device Identification and I2C Settings
Description Bit Name Configurable
I2C slave ID (7-bit)

Device I2C address

 - No
Refer to

TRM for default value.

Table 3-6 lists device settings for interrupts. When interrupt from an event is unmasked, an interrupt is generated to nINT pin.

Table 3-6 Interrupt Mask Settings
Interrupt event Bit Name Configurable
General Sync clock appears or disappears SYNC_CLK_MASK Yes
Thermal warning TDIE_WARN_MASK Yes
Load measurement ready I_LOAD_READY_MASK Yes
Register reset RESET_REG_MASK Yes
BUCK0 Buck0 PGOOD has reached threshold level BUCK0_PG_MASK Yes
Buck0 current limit triggered BUCK0_ILIM_MASK Yes
BUCK1 Buck1 PGOOD has reached threshold level BUCK1_PG_MASK Yes
Buck1 current limit triggered BUCK1_ILIM_MASK Yes
BUCK2 Buck2 PGOOD has reached threshold level BUCK2_PG_MASK Yes
Buck2 current limit triggered BUCK2_ILIM_MASK Yes
BUCK3 Buck3 PGOOD has reached threshold level BUCK3_PG_MASK Yes
Buck3 current limit triggered BUCK3_ILIM_MASK Yes