SNVU590A October   2018  – July 2025 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  6. 3Configuration
    1. 3.1 Configuration Sequence
    2. 3.2 Default OTP Configurations
    3. 3.3 Recommended Order of Configuring Registers Through I2C
      1. 3.3.1 Voltage Settings
      2. 3.3.2 Current Limit and Other Regulator Settings
      3. 3.3.3 GPO Settings
      4. 3.3.4 Clock Sync Functions
      5. 3.3.5 PGOOD Settings
      6. 3.3.6 Interrupt Settings
      7. 3.3.7 Startup and Shutdown Sequence
      8. 3.3.8 Set ENx Pin Control Bits
      9. 3.3.9 Set EN_BUCKx Bits
  7. 4Revision History

3.3.7 Startup and Shutdown Sequence

Each of the bucks and GPOs on the LP8756x-Q1 can be set to startup and shutdown in a specific sequence. To configure the desired sequence the STARTUP_DELAY and SHUTDOWN_DELAY fields for each output need to be set to a value between 0x0 and 0xF. The delay time that this value corresponds to depends on the DOUBLE_DELAY bit and the HALF_DELAY bit located in the CONFIG register. A value of 0 on both of these bits allow a delay ranging from 0ms to 15ms with 1ms steps. Figure 3-4 shows an example of how these delays can be used to configure a startup and shutdown sequence, in this case with EN1 signal. For a full description of all registers and their settings, see the device-specific data sheet.

LP875610-Q1 LP875620-Q1 LP875630-Q1 LP875640-Q1 LP875650-Q1 Startup and Shutdown Sequence Timing Diagram Figure 3-4 Startup and Shutdown Sequence Timing Diagram