SNVU590A October   2018  – July 2025 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  6. 3Configuration
    1. 3.1 Configuration Sequence
    2. 3.2 Default OTP Configurations
    3. 3.3 Recommended Order of Configuring Registers Through I2C
      1. 3.3.1 Voltage Settings
      2. 3.3.2 Current Limit and Other Regulator Settings
      3. 3.3.3 GPO Settings
      4. 3.3.4 Clock Sync Functions
      5. 3.3.5 PGOOD Settings
      6. 3.3.6 Interrupt Settings
      7. 3.3.7 Startup and Shutdown Sequence
      8. 3.3.8 Set ENx Pin Control Bits
      9. 3.3.9 Set EN_BUCKx Bits
  7. 4Revision History

1 Introduction

The LP8756x-Q1 contains four step-down DC/DC converter cores, which are configured as 4-phase single output, 3-phase and single phase outputs, one dual phase and two single phase outputs, four single phase outputs or two dual phase outputs. The device is controlled by an I2C-compatible serial interface and by enable signals. Typically the settings such as output voltages, startup/shutdown sequences etc. for the LP8756x-Q1 PMIC are programmed during IC manufacturing by a one time programmable memory (OTP). However, with an MCU this device can also be configured after each start up to fit different design requirements. Default values for the configuration registers (volatile memory) are loaded from the OTP during device power-up, and through I2C bus the registers can be updated to desired values.

This document explains how to set up an LP8756x-Q1 PMIC to be configured at start up so that it can be used in different designs, without the need for a new OTP. Specific OTP versions described in this document have been designed to allow the PMIC to be easily configured at each power-up. For device specifications and detailed functionality, see the device-specific data sheet.