1 Introduction

Figure 1-1 shows a typical single phase three-level I-Type inverter, named neutral point clamped (NPC) inverter. The single phase NPC inverter includes 4 FETs, like IGBT, in series, where S1 and S4 are called outer switches, with S2 and S3 called inner switches.

Considering the difference between positive cycle and negative cycle when tied to the grid, the general switching states of four FETs in normal operation are shown in Table 1-1.

There are several events which lead to quick shut-down to protect the semiconductors and the system, like over current, thermal overload, etc. Unlike immediately switching off all the FETs simultaneously in two level inverter, for three-level inverter, it must be made sure that the correct switch-off sequence is maintained: outer switches (S1 or S4) off first, inner switches (S2 or S3) off after a specific delay, while the inner one must be switched on firstly during the recover process. This delayed protection requirement has been a challenge for lots of UPS or solar inverter customers for a long time. Since using software algorithms will cause too much delay to provide in-time protection, some customers have to use external hardware circuits, like FPGA or CPLD, to achieve such protection logic, which increases the system cost and also the development effort.

This application report demonstrates how to implement delayed protection with existed Type 4 ePWM features that are available in all new C2000 devices, including F2838xD/S, F2837xD/S, F2807x and F28004x. In the Type 4 EPWM module, the Action Qualifier sub-module includes two additional trigger events (T1 and T2), which can be sourced from comparator, trip or sync events, together with Dead-Band sub-module, make it possible to add customized delay time to tripped/fault signals.