SPRAD06C March   2022  â€“ March 2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM62L

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
      3. 1.4.3 Return Current Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2DDR4 Board Design and Layout Guidance
    1. 2.1  DDR4 Introduction
    2. 2.2  DDR4 Device Implementations Supported
    3. 2.3  DDR4 Interface Schematics
      1. 2.3.1 DDR4 Implementation Using 16-Bit SDRAM Devices
      2. 2.3.2 DDR4 Implementation Using 8-Bit SDRAM Devices
    4. 2.4  Compatible JEDEC DDR4 Devices
    5. 2.5  Placement
    6. 2.6  DDR4 Keepout Region
    7. 2.7  DBI
    8. 2.8  VPP
    9. 2.9  Net Classes
    10. 2.10 DDR4 Signal Termination
    11. 2.11 VREF Routing
    12. 2.12 VTT
    13. 2.13 POD Interconnect
    14. 2.14 CK and ADDR_CTRL Topologies and Routing Guidance
    15. 2.15 Data Group Topologies and Routing Guidance
    16. 2.16 CK and ADDR_CTRL Routing Specification
      1. 2.16.1 CACLM - Clock Address Control Longest Manhattan Distance
      2. 2.16.2 CK and ADDR_CTRL Routing Limits
    17. 2.17 Data Group Routing Specification
      1. 2.17.1 DQLM - DQ Longest Manhattan Distance
      2. 2.17.2 Data Group Routing Limits
    18. 2.18 Bit Swapping
      1. 2.18.1 Data Bit Swapping
      2. 2.18.2 Address and Control Bit Swapping
  6. 3LPDDR4 Board Design and Layout Guidance
    1. 3.1  LPDDR4 Introduction
    2. 3.2  LPDDR4 Device Implementations Supported
    3. 3.3  LPDDR4 Interface Schematics
    4. 3.4  Compatible JEDEC LPDDR4 Devices
    5. 3.5  Placement
    6. 3.6  LPDDR4 Keepout Region
    7. 3.7  LPDDR4 DBI
    8. 3.8  Net Classes
    9. 3.9  LPDDR4 Signal Termination
    10. 3.10 LPDDR4 VREF Routing
    11. 3.11 LPDDR4 VTT
    12. 3.12 CK0 and ADDR_CTRL Topologies
    13. 3.13 Data Group Topologies
    14. 3.14 CK0 and ADDR_CTRL Routing Specification
    15. 3.15 Data Group Routing Specification
    16. 3.16 Byte and Bit Swapping
  7. 4LPDDR4 Board Design Simulations
    1. 4.1 Board Model Extraction
    2. 4.2 Board-Model Validation
    3. 4.3 S-Parameter Inspection
    4. 4.4 Time Domain Reflectometry (TDR) Analysis
    5. 4.5 System Level Simulation
      1. 4.5.1 Simulation Setup
      2. 4.5.2 Simulation Parameters
      3. 4.5.3 Simulation Targets
        1. 4.5.3.1 Eye Quality
        2. 4.5.3.2 Delay Report
        3. 4.5.3.3 Mask Report
    6. 4.6 Design Example
      1. 4.6.1 Stack-Up
      2. 4.6.2 Routing
      3. 4.6.3 Model Verification
      4. 4.6.4 Simulation Results
  8. 5Additional Information: Package Delays
  9. 6Summary
  10. 7References
  11. 8Revision History

1.4.2 High-Speed Bypass Capacitors

High-speed (HS) bypass capacitors are critical for proper DDR interface operation. This is particularly important to minimize the parasitic series inductance of the HS bypass capacitors to VDDS_DDR and the associated ground connections. Table 1-3 contains the specification for the HS bypass capacitors and for the power connections on the PCB. Generally speaking, TI recommends:

  • Fitting as many HS bypass capacitors as possible.
  • Minimizing the distance from the bypass capacitor to the pins and balls being bypassed.
  • Using the smallest physical sized ceramic capacitors possible with the highest capacitance readily available.
  • Connecting the bypass capacitor pads to the vias using the widest traces possible and using the largest via hole size possible.
  • Minimizing via sharing. Note the limits on via sharing shown in Table 1-3.
  • Using three-terminal capacitors instead of two terminal capacitors. Three-terminal capacitors provide lower loop inductance, and one three-terminal capacitor can take the place of multiple two-terminal capacitors, further optimizing loop inductance.

For any additional SDRAM requirements, see the manufacturer's data sheet.

Table 1-3 High-Speed Bypass Capacitors
Parameter MIN TYP MAX UNIT
HS bypass capacitor package size (1) 0201 0402 Mils
Distance, HS bypass capacitor to processor being bypassed (2)(3)(4) 150 Mils
Processor HS bypass capacitor count per VDDS_DDR rail(5) 5 Devices
Processor HS bypass capacitor total capacitance per VDDS_DDR rail(5) 1.4 uF
Number of connection vias for each device power/ground ball 1 Vias
Trace length from processor power/ground ball to connection via (2) 35 70 Mils
Distance, HS bypass capacitor to DDR device being bypassed (6) 150 Mils
DDR device HS bypass capacitor count Refer to DDR manufacturer guidelines
Number of connection vias for each HS capacitor (7)(8) 2 Vias
Trace length from bypass capacitor to connection via (2)(8) 35 100 Mils
Number of connection vias for each DDR device power/ground ball 1 Vias
Trace length from DDR device power/ground ball to connection via (2) 35 60 Mils
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer or shorter is preferable.
(3) Measured from the nearest processor power or ground ball to the center of the capacitor package.
(4) Three of these capacitors need to be located underneath the processor, among the cluster of VDDS_DDR balls.
(5) Decoupling capacitor counts and capacitor values need to be derived from power aware PCB simulations. The PCB designer has a responsibility to make sure that any design meets the provided PDN targets.
(6) Measured from the DDR device power or ground ball to the center of the capacitor package. Refer to the guidance from the SDRAM manufacturer.
(7) An additional HS bypass capacitor can share the connection vias only if the bypass is mounted on the opposite side of the board. No sharing of vias is permitted on the same side of the board.
(8) An HS bypass capacitor can share a via with a DDR device mounted on the same side of the PCB. A wide trace must be used for the connection, and the length from the capacitor pad to the DDR device pad needs to be less than 150 mils.