SPRUIY9C May   2021  – December 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
  6. 2Hardware
    1. 2.1 EVM Revisions and Assembly Variants
    2. 2.2 Important Usage Notes
    3. 2.3 System Description
      1. 2.3.1 Functional Block Diagram
      2. 2.3.2 Power-On/Off Procedures
        1. 2.3.2.1 Power-On Procedure
        2. 2.3.2.2 Power-Off Procedure
      3. 2.3.3 Peripheral and Major Component Description
        1. 2.3.3.1  Clocking
          1. 2.3.3.1.1 Ethernet PHY Clock
          2. 2.3.3.1.2 AM64x SoC Clock
        2. 2.3.3.2  Reset
        3. 2.3.3.3  Power
          1. 2.3.3.3.1 Power Input
          2. 2.3.3.3.2 USB Type-C Interface for Power Input
          3. 2.3.3.3.3 Power Fault Indication
          4. 2.3.3.3.4 Power Supply
          5. 2.3.3.3.5 Power Sequencing
          6. 2.3.3.3.6 Power Supply
        4. 2.3.3.4  Configuration
          1. 2.3.3.4.1 Boot Modes
        5. 2.3.3.5  JTAG
        6. 2.3.3.6  Test Automation
        7. 2.3.3.7  UART Interface
        8. 2.3.3.8  Memory Interfaces
          1. 2.3.3.8.1 LPDDR4 Interface
          2. 2.3.3.8.2 MMC Interface
            1. 2.3.3.8.2.1 Micro SD Interface
            2. 2.3.3.8.2.2 WiLink Interface
            3. 2.3.3.8.2.3 OSPI Interface
            4. 2.3.3.8.2.4 Board ID EEPROM Interface
        9. 2.3.3.9  Ethernet Interface
          1. 2.3.3.9.1 DP83867 PHY Default Configuration
          2. 2.3.3.9.2 DP83867 – Power, Clock, Reset, Interrupt and LEDs
          3. 2.3.3.9.3 Industrial Application LEDs
        10. 2.3.3.10 USB 3.0 Interface
        11. 2.3.3.11 PRU Connector
        12. 2.3.3.12 User Expansion Connector
        13. 2.3.3.13 MCU Connector
        14. 2.3.3.14 Interrupt
        15. 2.3.3.15 I2C Interface
        16. 2.3.3.16 IO Expander (GPIOs)
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 Regulatory Compliance
  9. 5Additional Information
    1. 5.1 Known Issues
      1. 5.1.1 Issue 1: LP8733x Max output Capacitance Spec Exceeded on LDO0 and LDO1
      2. 5.1.2 Issue 2: LP8733x Output Voltage of 0.9V Exceeds AM64x VDDR_CORE max Voltage Spec of 0.895 V
      3. 5.1.3 Issue 3 - SDIO Devices on MMC0 Require Careful Trace Lengths to Meet Interface Timing Requirements
      4. 5.1.4 Issue 4 - LPDDR4 Data Rate Limitation in Stressful Conditions
      5. 5.1.5 Issue 5 - Junk Character
      6. 5.1.6 Issue 6 - Test Power Down Signal Floating
      7. 5.1.7 Issue 7 - uSD Boot Not Working
    2.     Trademarks
    3.     65
  10. 6Revision History

1.1 Introduction

This evaluation module user’s guide describes the hardware architecture of the AM64x SKEVM. The AM64x processor comprises of a Dual-Core 64-bit Arm® Cortex®-A53 microprocessor, 2x Dual core Arm Cortex-R5F MCUs and an Arm Cortex-M4F MCU.

The AM64x starter kit is a stand-alone test and development platform that is an excellent choice for accelerating the prototype phase of the next design. The kit includes: wired and wireless connectivity, three expansion headers, multiple boot options and flexible debug capabilities.

The starter kit is equipped with AM64x processor from TI and an optimized feature-set to allow the user to create commercial and industrial devices using Ethernet-based, USB, and serial wired interfaces plus 2.4-GHz and 5-GHz wireless communications. Two 1-Gbps Ethernet Ports for wired connectivity are on-board, in addition to three expansion headers (PRU, MCU, User) headers to expand the functionality of the board. Using standard serial protocols such as UART, I2C, and SPI, the starter kit can interface with a multitude of other devices, acting as a communications gateway. Receiving 5-V power from a standard USB-C port, the starter kit allows the user to access the R5F cores of the AM64x; making the device an excellent choice as a programmable logic controller (PLC) or motor controller, processing sensor inputs and managing peripherals in real-time while running Linux on the A53 cores, and making the device the central engine in a remote industrial communication network. The embedded emulation logic allows for emulation and debugging using standard development tools such as Code Composer Studio™ from TI.

Note: This evaluation board is a pre-production release and has several known issues that must not be copied into a production system. For detailed information, see Section 5.1.

During custom board design, customers tend to reuse the SK design files and make edits to the design file. Alternatively, customers reuse some of the common implementations including the SOC, memory and communication interfaces. Since the SK is expected to have additional functionalities, customers optimize the SK implementation to suit their board design requirements. While optimizing the SK schematics, errors get introduced into the custom design that could cause functional, performance or reliability issues. When optimizing customers have queries regarding the SK implementation resulting in design errors. Many of the optimization and design errors are common across designs. Based on the learnings and data sheet pin connectivity recommendations, comprehensive Design Notes (D-Note:), Review Notes (R-Note:) and Cad Notes (Cad Note:) have been added near each section of the SK schematic that customers could review and follow to minimize errors. Additional files as part of the design downloads have been included to support customer evaluation.