SPRUJH3 April   2025 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280023 , TMS320F280023C , TMS320F280025 , TMS320F280025C , TMS320F280034 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037C , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039C , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049C , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379S , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Configuring the Boot Mode
    1. 2.1 Standalone Boot
      1. 2.1.1 Boot Mode Select Pins (BMSP)
      2. 2.1.2 Boot Definition Table (BOOTDEF)
      3. 2.1.3 Boot ROM OTP Configuration Registers
      4. 2.1.4 CPU2 Boot Flow
    2. 2.2 Emulation Boot
  6. 3Programming the Flash
    1. 3.1 Flash API
    2. 3.2 Flash Kernels
  7. 4Bootloading Code to Flash
    1. 4.1 C2000 Hex Utility
    2. 4.2 Common Boot Modes
      1. 4.2.1 Boot to Flash
      2. 4.2.2 SCI Boot
      3. 4.2.3 CAN Boot
      4. 4.2.4 CAN-FD Boot
      5. 4.2.5 USB Boot
  8. 5FAQ
    1. 5.1 Selecting the BMSP GPIOs with a Software-based Implementation
    2. 5.2 Running a Flash Kernel from the Flash Instead of the RAM
    3. 5.3 No Symbols Defined When Debugging Boot ROM
    4. 5.4 Writing Values in the OTP Using the On-Chip Flash Tool
    5. 5.5 Writing Values in the OTP Using the Flash API Plugin
  9. 6Summary
  10. 7References

2.1.1 Boot Mode Select Pins (BMSP)

The Boot Mode Select Pins (BMSPs) are decoded by the device and used to index the boot definition table, determining which boot mode to execute. Besides the default boot configurations available on every device, users can opt for other BMSPs and boot modes by programming the OTP memory. While the memory contents for a ROM are determined at manufacturing time, the OTP can be programmed only once after production allowing for more flexibility in applications where reliable and repeatable reading of data is required.

In the context of standalone boot loading, programming the OTP is required when:

  1. A boot option is not supported by the default boot options
  2. Different GPIOs are required for the peripherals or BMSPs
  3. Different entry point to the application is required
  4. The flexibility of using multiple boot options is required

Depending on the device families (as listed in Table 2-3), the BMSPs can be modified by writing to the respective BOOTPIN-CONFIG or BOOTCTRL memory locations in the user-configurable Dual Code Security Module (DCSM) OTP [7].

Note: In the DCSM, there are two independent secure zones to which securable resources can be assigned – Zone 1 (Z1) and Zone 2 (Z2). The security module restricts the CPU access to on-chip secure memory and resources without interrupting or stalling CPU execution. When a read occurs to a secure memory location, the read returns a zero value and CPU execution continues with the next instruction. This, in effect, blocks read and write access to secure memories through the JTAG port. Note that insecure resources can still be accessed by the JTAG debugger.

The BOOTPIN-CONFIG register is a 32-bit wide location consisting of four 8-bit wide partitions. Three partitions are designated for the BMSPs and the final partition is a key that designates validity of the OTP configuration. This register can be found in the DCSM OTP as Z1-OTP-BOOTPIN-CONFIG and Z2-OTP-BOOTPIN-CONFIG depending on which zone is being configured.

Note: The configurations programmed in Z2 take priority over the configurations in Z1. Therefore, TI recommends to use the Z1 location first and then Z2 next if the OTP configurations need to be altered.

The BOOTPIN-CONFIG registers in the DCSM OTP can be programmed using the On-Chip Flash tool in CCS or Flash API (see Section 5.4 or Section 5.5, respectively for steps), or graphically with the DCSM tool in SysConfig [8].

Table 2-3 Boot Configuration Type Per Device Family
BOOTPIN-CONFIG and BOOTDEF Devices BOOTCTRL Devices
F28002x,
F28003x,
F28004x,
F280013x,
F280015x,
F2838x,
F28P55x,
F28P65x		 F2807x,
F2837xD,
F2837xS

The BMSPs can be set to almost any GPIO (see the Configuring Boot Mode Pins chapter in the device-specific TRM for exceptions) to be used during boot up, where GPIO0 is 0x0, GPIO1 is 0x01, and so on. Although the BMSPs need to be manually pulled high or low with the external GPIO pins in most cases, a software-controlled firmware update is possible following the method described in Section 5.1.

The BMSPs can also be used in both the boot ROM and the application afterward (with alternate functionality) as long as the hold time for boot-mode pins is not violated (see Reset - XRSn - Timing Requirements in the data sheet) [29].

Note: However, if a LaunchPad™ or controlCard is being used, then the default BMSPs are manually pulled up/down with the external boot switches and cannot be safely used in an application after.

The number of BMSPs used either expands or restricts the potential boot modes selectable in the boot table exponentially. If three BMSPs are used, then up to 8 boot options are selectable. Reducing to two BMSPs means only four boot options are available. Using zero BMSPs means that a single boot option is automatically selected, eliminating the need for external manipulation of the GPIOs as well as freeing up other pins needed to be repurposed for boot pins.

Disabling any particular BMSP can be achieved by writing 0xFF to the same BOOTPIN-CONFIG memory location as when changing the GPIO number used. When decoding the boot mode, BMSP0 is the least-significant bit and BMSP2 is the most-significant bit of the boot table index value. TI recommends to start with disabling BMSP2 when disabling BMSPs.

In standalone boot, if the Z1 or Z2 OTP loaded registers are not written to with the correct BOOTPIN-CONFIG_KEY (0x5A) designating register validity, then the default BMSPs are decoded to index the default boot table.

Table 2-4 BOOTPIN-CONFIG Bit Fields
Bit Name Description
31:24 Key Write 0x5A to these 8-bits to tell the boot ROM code that the bits in this register are valid.
23:16 Boot Mode Select Pin 2 (BMSP2) Refer to BMSP0 description.
15:8 Boot Mode Select Pin 1 (BMSP1) Refer to BMSP0 description.
7:0 Boot Mode Select Pin 0 (BMSP0)

Set to the GPIO pin to be used during boot (up to 255).

0x0 = GPIO0, 0x01 = GPIO1, and so on.

Writing 0xFF disables this BMSP and this pin is no longer used to select the boot mode.
Note: In the case when BMSP2 is only used (BMSP1 and BMSP0 are disabled), then only the boot table indexes of 0 and 4 are selectable. In the case when BMSP0 is only used, then the selectable boot table indexes are 0 and 1. This is important to keep in mind when programming the boot options in the boot table as each BMSP still maintains positional weight regardless of the condition of the other BMSPs.
Note:

Devices that use the BOOTCTRL register (see Table 2-3) have a different boot flow and configuration from the device families that use the BOOTPIN-CONFIG register.

When programmed with a valid key, the BOOTCTRL register allows for different GPIOs to be used as the two-boot mode select pins. The total customizable BMSPs for BOOTCTRL devices is fixed at two, as opposed to the maximum of three for BOOTPIN-CONFIG devices. However, the same GPIO can be assigned to both BMSPs, allowing for a single pin use case on all devices.

Please see the device-specific TRM for more details on the BOOTCTRL register.