SPRUJH3 April   2025 TMS320F2800132 , TMS320F2800133 , TMS320F2800135 , TMS320F2800137 , TMS320F2800152-Q1 , TMS320F2800153-Q1 , TMS320F2800154-Q1 , TMS320F2800155 , TMS320F2800155-Q1 , TMS320F2800156-Q1 , TMS320F2800157 , TMS320F2800157-Q1 , TMS320F280021 , TMS320F280023 , TMS320F280023C , TMS320F280025 , TMS320F280025C , TMS320F280034 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037C , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039C , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041C , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049C , TMS320F28076 , TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28378D , TMS320F28378S , TMS320F28379D , TMS320F28379S , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P550SG , TMS320F28P550SJ , TMS320F28P559SG-Q1 , TMS320F28P559SJ-Q1 , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Configuring the Boot Mode
    1. 2.1 Standalone Boot
      1. 2.1.1 Boot Mode Select Pins (BMSP)
      2. 2.1.2 Boot Definition Table (BOOTDEF)
      3. 2.1.3 Boot ROM OTP Configuration Registers
      4. 2.1.4 CPU2 Boot Flow
    2. 2.2 Emulation Boot
  6. 3Programming the Flash
    1. 3.1 Flash API
    2. 3.2 Flash Kernels
  7. 4Bootloading Code to Flash
    1. 4.1 C2000 Hex Utility
    2. 4.2 Common Boot Modes
      1. 4.2.1 Boot to Flash
      2. 4.2.2 SCI Boot
      3. 4.2.3 CAN Boot
      4. 4.2.4 CAN-FD Boot
      5. 4.2.5 USB Boot
  8. 5FAQ
    1. 5.1 Selecting the BMSP GPIOs with a Software-based Implementation
    2. 5.2 Running a Flash Kernel from the Flash Instead of the RAM
    3. 5.3 No Symbols Defined When Debugging Boot ROM
    4. 5.4 Writing Values in the OTP Using the On-Chip Flash Tool
    5. 5.5 Writing Values in the OTP Using the Flash API Plugin
  9. 6Summary
  10. 7References

2.1.3 Boot ROM OTP Configuration Registers

The boot ROM code involves numerous memory addresses and registers used during execution, supporting boot configurations from DCSM Zone 1 (Z1) and Zone 2 (Z2) registers. The user-configurable DCSM OTP locations used in the standalone boot flow can only be programmed once. The configuration of these registers is detailed in Section 2.1.

In the DCSM context, BOOTPIN-CONFIG maps to GPREG1, and BOOTDEF-LOW/BOOTDEF-HIGH map to GPREG3/GPREG4 respectively. Table 2-7 provides these locations.

Section 5.4 and Section 5.5 detail how to program the DCSM OTP with the On-Chip Flash Tool and Flash API respectively, following example use cases. SysConfig can also be used to program the DCSM OTP with an intuitive graphical user-interface (GUI) [8].

Note: The register addresses in Table 2-7 are for the F280015x family of devices. Device specific information can be found in the Boot ROM chapter's Boot ROM Registers table in the Technical Reference Manual (TRM).
Table 2-7 F280015x Boot ROM Registers
Boot Flow Register Name Boot ROM Name Register Address User OTP Address
Standalone
(Using Z1)		 Z1-GPREG1 Z1-OTP-BOOTPIN-CONFIG 0x0005 F008 0x0007 8008
Z1-GPREG2 Z1-OTP-BOOT-GPREG2 0x0005 F00A 0x0007 800A
Z1-GPREG3 Z1-OTP-BOOTDEF-LOW 0x0005 F00C 0x0007 800C
Z1-GPREG4 Z1-OTP-BOOTDEF-HIGH 0x0005 F00E 0x0007 800E
Standalone
(Using Z2)		 Z2-GPREG1 Z2-OTP-BOOTPIN-CONFIG 0x0005 F088 0x0007 8208
Z2-GPREG2 Z2-OTP-BOOT-GPREG2 0x0005 F08A 0x0007 820A
Z2-GPREG3 Z2-OTP-BOOTDEF-LOW 0x0005 F08C 0x0007 820C
Z2-GPREG4 Z2-OTP-BOOTDEF-HIGH 0x0005 F08E 0x0007 820E