TIDU312A May   2014  – November 2020

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 PFC Stage Implementation
    2. 1.2 BL PFC Electrical Specifications
  3. 2Software Overview
    1. 2.1 Software Control Flow
    2. 2.2 Incremental Builds
  4. 3Procedure for Running the Incremental Builds
    1. 3.1 Build 1: Open-Loop Boost With ADC Measurements
      1. 3.1.1 Build 1 Objective
      2. 3.1.2 Build 1 Overview
      3. 3.1.3 Build 1 Protection
      4. 3.1.4 Build 1 Procedure
        1. 3.1.4.1 Step 1.1: Start CCS and Open a Project
        2. 3.1.4.2 Step 1.2: Device Initialization, Main, and ISR Files
        3. 3.1.4.3 Step 1.3: Build and Load the Project
        4. 3.1.4.4 Step 1.4: Debug the Environment Windows
          1. 3.1.4.4.1 Step 1.5: Use Real-Time Emulation
          2. 3.1.4.4.2 Step 1.6: Run the Code for Build 1
    2. 3.2 Build 2: BL PFC With Closed-Current Loop
      1. 3.2.1 Build 2 Objective
      2. 3.2.2 Build 2 Overview
      3. 3.2.3 Build 2 Procedure
        1. 3.2.3.1 Step 2.1: Build and Load Project
    3. 3.3 Build 3: BL PFC With Closed Voltage and Current Loop
      1. 3.3.1 Build 3 Objective
      2. 3.3.2 Build 3 Overview
      3. 3.3.3 Build 3 Procedure
        1. 3.3.3.1 Step 3.1: Build and Load Project
  5. 4Test Results
  6. 5References
  7. 6Revision History

3.3.2 Build 3 Overview

Figure 3-6 shows the software blocks used in this build. Compared to build 2 in Figure 3-5 this build uses an additional 2p2z control block labeled as CNTL_2P2Z:2. This is the 2nd instantiation of the 2p2z control block in order to implement the BL PFC voltage loop control. This voltage loop controller is executed at 50kHz rate which is half the rate for current loop. The output from this control block drives the input node VpfcVcmd of the PFC_BL_ICMD block. This is the main difference compared to build 2 where VpfcVcmd is updated by user from CCS watch window in an open voltage loop mode.

GUID-ED718E5E-F2C7-41EF-9EAA-1C1E7FA4E29E-low.gifFigure 3-6 Build 3 Software Blocks

Similar to current loop controller, this voltage loop controller, CNTL_2P2Z:2, also requires five control coefficients. These coefficients and the clamped output of the controller are stored as the elements of a 2nd structure named CNTL_2P2Z_CoefStruct2. The coefficients for this controller can be changed directly by modifying the values for B0, B1, B2, A1, and A2 inside the structure CNTL_2P2Z_CoefStruct2, or by changing the equivalent PID gains as discussed in Section 3.2.

Start-up, Inrush Current Control, and Slew-limit

At start-up, the controller monitors the PFC DC bus voltage. When this voltage reaches a minimum level (default setting around 100Vdc) the inrush relay control circuit is activated to bypass the inrush current control resistor. Following this the PFC action is enabled and the output DC bust slowly ramps up to the desired value of about 400Vdc. This ramp up speed is set by the parameter VbusSlewRate defined and implemented in the soft-start state machine task C2. This part of the software can be quickly modified to implement any other desired mode for PFC start-up.