TIDUD61E October   2020  – April 2021

 

  1.   Description
  2.   Resources
  3.   Features
  4.   Applications
  5.   5
  6. 1System Description
    1. 1.1 Key System Specifications
  7. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
      1. 2.2.1 Input AC Voltage Sensing
      2. 2.2.2 Bus Voltage Sensing
      3. 2.2.3 AC Current Sensing
      4. 2.2.4 Sense Filter
      5. 2.2.5 Protection (CMPSS)
    3. 2.3 Highlighted Products
      1. 2.3.1 C2000™ MCU F28004x
      2. 2.3.2 LMG3410R070
      3. 2.3.3 UCC27714
    4. 2.4 System Design Theory
      1. 2.4.1 PWM
      2. 2.4.2 Current Loop Model (PFC and Inverter mode)
      3. 2.4.3 DC Bus Regulation Loop (for PFC mode only)
      4. 2.4.4 Soft Start Around Zero Crossing for Eliminate or Reduce Current Spike
      5. 2.4.5 AC Drop Test
  8. 3Hardware, Software, Testing Requirements, and Test Results
    1. 3.1 Required Hardware and Software
      1. 3.1.1 Hardware
        1. 3.1.1.1 Base Board Settings
        2. 3.1.1.2 Control Card Settings
      2. 3.1.2 Software
        1. 3.1.2.1 Opening Project Inside CCS
        2. 3.1.2.2 Project Structure
        3. 3.1.2.3 Using CLA on C2000 MCU to Alleviate CPU Burden
        4. 3.1.2.4 CPU and CLA Utilization and Memory Allocation
        5. 3.1.2.5 Running the Project
          1. 3.1.2.5.1 Lab 1: Open Loop, DC (PFC Mode)
            1. 3.1.2.5.1.1 Setting Software Options for LAB 1
            2. 3.1.2.5.1.2 Building and Loading Project
            3. 3.1.2.5.1.3 Setup Debug Environment Windows
            4. 3.1.2.5.1.4 Using Real-Time Emulation
            5. 3.1.2.5.1.5 Running Code
          2. 3.1.2.5.2 Lab 2: Closed Current Loop DC (PFC)
            1. 3.1.2.5.2.1 Setting Software Options for Lab 2
            2. 3.1.2.5.2.2 Designing Current Loop Compensator
            3. 3.1.2.5.2.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.2.4 Running Code
          3. 3.1.2.5.3 Lab 3: Closed Current Loop, AC (PFC)
            1. 3.1.2.5.3.1 Setting Software Options for Lab 3
            2. 3.1.2.5.3.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.3.3 Running Code
          4. 3.1.2.5.4 Lab 4: Closed Voltage and Current Loop (PFC)
            1. 3.1.2.5.4.1 Setting Software Options for Lab 4
            2. 3.1.2.5.4.2 Designing Voltage Loop Compensator
            3. 3.1.2.5.4.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.4.4 Running Code
          5. 3.1.2.5.5 Lab 5: Open loop, DC (Inverter)
            1. 3.1.2.5.5.1 Setting Software Options for Lab 5
            2. 3.1.2.5.5.2 Building and Loading Project
            3. 3.1.2.5.5.3 Setup Debug Environment Windows
            4. 3.1.2.5.5.4 Running Code
          6. 3.1.2.5.6 Lab 6: Open loop, AC (Inverter)
            1. 3.1.2.5.6.1 Setting Software Options for Lab 6
            2. 3.1.2.5.6.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.6.3 Running Code
          7. 3.1.2.5.7 Lab 7: Closed Current Loop, DC (Inverter with resistive load)
            1. 3.1.2.5.7.1 Setting Software Options for Lab 7
            2. 3.1.2.5.7.2 Designing Current Loop Compensator
            3. 3.1.2.5.7.3 Building and Loading Project and Setting up Debug
            4. 3.1.2.5.7.4 Running Code
          8. 3.1.2.5.8 Lab 8: Closed Current Loop, AC (Inverter with resistive load)
            1. 3.1.2.5.8.1 Setting Software Options for Lab 8
            2. 3.1.2.5.8.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.8.3 Running Code
          9. 3.1.2.5.9 Lab 9: Closed Current Loop (Grid Connected Inverter)
            1. 3.1.2.5.9.1 Setting Software Options for Lab 9
            2. 3.1.2.5.9.2 Building and Loading Project and Setting up Debug
            3. 3.1.2.5.9.3 Running Code: Emulated Grid-tied Condition (Verification purpose only)
            4. 3.1.2.5.9.4 Running Code: Grid-tied Condition
        6. 3.1.2.6 Running Code on CLA
        7. 3.1.2.7 Advanced Options
          1. 3.1.2.7.1 Input Cap Compensation for PF Improvement Under Light Load
          2. 3.1.2.7.2 83
          3. 3.1.2.7.3 Adaptive Dead Time for Efficiency Improvements
          4. 3.1.2.7.4 Phase Shedding for Efficiency Improvements
          5. 3.1.2.7.5 Non-Linear Voltage Loop for Transient Reduction
          6. 3.1.2.7.6 Software Phase Locked Loop Methods: SOGI - FLL
    2. 3.2 Testing and Results
      1. 3.2.1 Test Results at Input 120 Vrms, 60 Hz, Output 380-V DC
        1. 3.2.1.1 Startup
        2. 3.2.1.2 Steady State Condition
        3. 3.2.1.3 Transient Test With Step Load Change
          1. 3.2.1.3.1 0% to 50% Load Step Change
          2. 3.2.1.3.2 50% to 100% Load Step Change
          3. 3.2.1.3.3 100% to 50% Load Step Change
          4. 3.2.1.3.4 50% to 100% Load Step Change
      2. 3.2.2 Test Results at Input 230 Vrms, 50 Hz, Output 380 V DC
        1. 3.2.2.1 Startup
        2. 3.2.2.2 Steady State Condition
        3. 3.2.2.3 Transient Test With Step Load Change
          1. 3.2.2.3.1 33% to 100% Load Step Change
          2. 3.2.2.3.2 100% to 33% Load Step Change
      3. 3.2.3 Test Results Graphs
  9. 4Design Files
    1. 4.1 Schematics
    2. 4.2 Bill of Materials
    3. 4.3 PCB Layout Recommendations
      1. 4.3.1 Layout Prints
    4. 4.4 Altium Project
    5. 4.5 Gerber Files
    6. 4.6 Assembly Drawings
  10. 5Software Files
  11. 6Related Documentation
    1. 6.1 Trademarks
  12. 7About the Author
  13. 8Revision History
Phase Shedding for Efficiency Improvements

Phase shedding can be an effective technique to improve efficiency in interleaved application by optimizing for the conduction and the switching losses. In this design there are three phases, so three different configurations are possible as shown in Figure 3-50.

GUID-EE3902BD-BE16-4128-9A7F-D8166EF5C4A8-low.gifFigure 3-50 Phase Shedding Options on TTPL PFC

In each of these modes the phase shift between each of them must be adjusted. When in two-phase mode, a 180° phase shift is desired between the PWMs, and when in three-phase mode, a 120° of phase shift is desired.

The decision to do phase shedding can be made on different parameters, such as the RMS current, power, the peak inductor current, and so on. When using RMS current the change of phases can be significantly delayed. Figure 3-51 shows phase shedding when the decision is based on RMS current. Code takes multiple AC cycles before the phases are added .

GUID-4235D818-CF74-4767-9501-70CD8E960D41-low.gifFigure 3-51 Waveform When Decision to Add Phases is Based on RMS Calculation

This delay may not be acceptable for many application. Thus, the voltage controller output is chosen as the decision point to drop or add phases. A state machine is constructed as shown in Figure 3-52, with some hysteresis built around the phase shedding points.

GUID-0E8FAB08-835B-406B-9004-580C7C35A6EE-low.gifFigure 3-52 State Machine for Phase Shedding Control

Bringing a phase in and out can cause in-advertent pulses to be generated. Hence the implementation to drop and add phase is done through the GPIO and PWM peripheral switch using the GPIO pin Mux registers. All PWM capable pins are configured and GPIO outputs and driven low. Now based on how many phases must be applied the GPIO pin mux is changed accordingly. It is safe to enable and disable the phases using the GPIO pin mux switch at any point in the AC cycle as the registers in the PWM are shadowed. Figure 3-53 shows details of the implementation of phase shedding on the C2000 MCU.

GUID-52910D53-67FC-4DE6-9983-B606E84F6300-low.gifFigure 3-53 Implementation of Phase Shedding on TTPL PFC Using C2000™ MCU

The phase shedding can be set in the powerSuite page by selecting enable under the Phase shedding option. The points at which phases are brought in and out are set by changing the PHASE_SHEDDING_1PH_2PH_TRANSITION_CURRENT and PHASE_SHEDDING_2PH_3PH_TRANSITION_CURRENT define, which correspond to I1 and I2 as shown in Figure 3-53. Recompile the code, load the code, and repeat the steps as outlined in Section 3.1.2.5.4 to test this feature. With this feature implemented, under transients the phases are dropped and added quickly.

Figure 3-54 and Figure 3-55 show the transient at 110 Vrms of 1.3 KW to 150 W and vice versa. The phases are added back quickly and dropped quickly under transients as the decision is based on the voltage loop generated current reference.

GUID-81E5BEAF-6F21-42D2-93DD-7F0F5C6D78AC-low.gifFigure 3-54 Phase Added Quickly Under Transient at 120 Vrms, 60 Hz
GUID-CF140F44-DA6F-46A9-BE00-D3211BEBB285-low.gifFigure 3-55 Phase Shed Quickly Under Transient at 120 Vrms, 60 Hz

Similarly at high line, a transient greater than 2 KW is applied, and the phase goes from single to three phase almost instantly. Figure 3-56 and Figure 3-56 show the test waveform at high line under transient of 2.16 KW to 150 W and vice versa.

GUID-DEE6B529-BC85-45AC-8756-AFAA81E17A13-low.gifFigure 3-56 Phase Added Quickly Under Transient at 230 Vrms, 50 Hz
GUID-4B6A40C0-BEDA-4E1C-B10B-65DC55749D47-low.gifFigure 3-57 Phase Shed Quickly Under Transient at 230 Vrms, 50 Hz

Figure 3-58 shows the efficiency improvement at 230 Vrms with phase shedding

GUID-25FDC43A-C4BD-4C83-A494-A49A24C87D1E-low.gifFigure 3-58 Efficiency Comparison at 230 Vrms With Phase Shedding and Without