DLPS269A March   2025  – June 2025 DLP991UUV

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 DMD Temperature Calculation
      1. 6.6.1 Off-State Thermal Differential (TDELTA_MIN)
      2. 6.6.2 On-State Thermal Differential (TDELTA_MAX)
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 DMD Die Temperature Sensing
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PCB Design Standards
      2. 9.1.2 General PCB Routing
        1. 9.1.2.1 Trace Impedance and Routing Priority
        2. 9.1.2.2 Example PCB Layer Stack-Up
        3. 9.1.2.3 Trace Width, Spacing
        4. 9.1.2.4 Power and Ground Planes
        5. 9.1.2.5 Trace Length Matching
          1. 9.1.2.5.1 HSSI Input Bus Skew
          2. 9.1.2.5.2 Other Timing Critical Signals
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

9.1.2.3 Trace Width, Spacing

Unless otherwise specified, TI recommends that all signals follow the 0.005"/0.0015" (Trace-Width/Spacing) design rule. Use an analysis of impedance and stack-up requirements to determine and calculate actual trace widths.

Maximize the width of all voltage signals as space permits.

Follow the width and spacing requirements listed in Table 9-5 and Table 9-6.

Table 9-5 Trace Minimum Spacing
SIGNAL PWR GND SINGLE-ENDED DIFFERENTIAL PAIRS UNIT
PAIR-TO-PAIR
PWR 15 5 15 15 mils
GND 5 5 5 mils
HSSI DMD Interface - DMD_D_(A,B,C,D)[7:0], DMD_DCLK_(A,B,C,D), 15 5 3x intra-pair (P-to-N) spacing 3x intra-pair (P-to-N) spacing mils
DMD LS Interface - DMD_LS_CLK, DMD_LS_WDATA, DMD_LS_RDATA_(A,B,C,D) 15 5 3x trace width spacing 3x intra-pair (P-to-N) spacing mils
All other signals 15 5 3x trace width spacing 3x intra-pair (P-to-N) spacing mils
Table 9-6 Voltage Trace Widths and Spacing Recommendations
SIGNAL NAME MIN. TRACE WIDTH (mils) MIN. TRACE SPACING (mils) LAYOUT REQUIREMENTS
GND Maximize 5 Maximize trace width to connecting pin as a minimum.
P3P3V 40 15 Create mini planes on layer 8 as needed. Connect to devices on layers 1 and 8 as necessary with multiple vias.
P1P9V 40 15 Create mini planes on layer 8 as needed. Connect to devices on layers 1 and 8 as necessary with multiple vias. Feedback resistor divider must be placed close to P1P9V load pins on DMD.
V_OFFSET (10V) 40 15 Create mini planes on layer 8 as needed. Connect to devices on layers 1 and 8 as necessary.
V_RESET (-14V) 40 15 Create mini planes on layer 8 as needed. Connect to devices on layers 1 and 8 as necessary.
V_BIAS (18V) 40 15 Create mini planes on layer 8 as needed. Connect to devices on layers 1 and 8 as necessary.