DLPS269A March   2025  – June 2025 DLP991UUV

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Requirements
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 DMD Temperature Calculation
      1. 6.6.1 Off-State Thermal Differential (TDELTA_MIN)
      2. 6.6.2 On-State Thermal Differential (TDELTA_MAX)
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
    3. 7.3 DMD Die Temperature Sensing
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 PCB Design Standards
      2. 9.1.2 General PCB Routing
        1. 9.1.2.1 Trace Impedance and Routing Priority
        2. 9.1.2.2 Example PCB Layer Stack-Up
        3. 9.1.2.3 Trace Width, Spacing
        4. 9.1.2.4 Power and Ground Planes
        5. 9.1.2.5 Trace Length Matching
          1. 9.1.2.5.1 HSSI Input Bus Skew
          2. 9.1.2.5.2 Other Timing Critical Signals
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
      2. 10.1.2 Device Markings
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

5.6 Electrical Characteristics

Over operating free-air temperature range and supply voltages (unless otherwise noted)
SYMBOLPARAMETER(2)(3)TEST CONDITIONS(2)MINTYPMAXUNIT
Current—Typical
IDDSupply current VDD(4)1.51.9A
IDDASupply current VDDA(4)1.41.9A
IOFFSETSupply current VOFFSET(5)(6)3750mA
IBIASSupply current VBIAS(5)(6)12.050mA
IRESETSupply current VRESET(6)–50–25mA
Power—Typical
PDDSupply power dissipation VDD(4)27103710mW
PDDASupply power dissipation VDDA(4)25003600mW
POFFSETSupply power dissipation VOFFSET(5)(6)370525mW
PBIASSupply power dissipation VBIAS(5)(6)216925mW
PRESETSupply power dissipation VRESET(6)350725mW
PTOTALSupply power dissipation Total61469485mW
LVCMOS Input
IILLow level input current(7)VDD = 1.95V , VI = 0V–100nA
IIHHigh level input current(7)VDD = 1.95V , VI = 1.95V135uA
LVCMOS Output
VOHDC output high voltage(8)IOH = –2mA0.8 × VDDV
VOLDC output low voltage(8)IOL = 2mA0.2 × VDDV
Receiver Eye Characteristics
A1Minimum eye opening(9)100400600mV
A2Maximum signal swing(9)(10)600mV
X1Maximum eye closure(9)0.275UI
X2Maximum eye closure(9)0.4UI
| tDRIFT |Drift between Clock and Data between Training Patterns20ps
Capacitance
CINInput capacitance LVCMOSf = 1MHz30pF
CINInput capacitance LSIF (low-speed interface)f = 1MHz20pF
CINInput capacitance HSSI (high-speed serial interface) - Differential - Clock and Data pinsf = 1MHz5pF
COUTOutput capacitancef = 1MHz10pF
(2) All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are required to operate the DMD.
(3) All voltage values are with respect to the ground pins (VSS).
(4) To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than the specified limit.
(5) To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than the specified limit.
(6) Power dissipation based upon 1 Phased reset, 1 array load, and 1 global reset in 90μs 
(7) The LVCMOS input specifications are for pin DMD_DEN_ARSTZ.
(8) The LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.
(9) Refer to Figure 5-10, Receiver Eye Mask (1e-12 BER).
(10) Defined in Section 5.4