DLPS269 Data sheet

DLPS269A March 2025 – June 2025 DLP991UUV

PRODUCTION DATA

5.4 Recommended Operating Conditions

Over operating free-air temperature range and supply voltages (unless otherwise noted) ⁽¹⁾

PARAMETER NAME		MIN	TYP	MAX	UNIT
Supply Voltages
V_DD	Supply voltage for LVCMOS core logic and low-speed interface (LSIF)⁽²⁾	1.85	1.9	1.95	V
V_DDA	Supply voltage for high-speed serial interface (HSSI) receivers⁽²⁾	1.85	1.9	1.95	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽²⁾⁽³⁾⁽⁴⁾	9.5	10	10.5	V
V_BIAS	Supply voltage for micromirror electrode⁽²⁾	17.5	18	18.5	V
V_RESET	Supply voltage for micromirror electrode⁽²⁾	–14.5	–14	–13.5	V
\| V_DDA – V_DD \|	Supply voltage delta, absolute value⁽⁵⁾			0.3	V
\| V_BIAS – V_OFFSET \|	Supply voltage delta, absolute value⁽⁶⁾			10.5	V
\| V_BIAS – V_RESET \|	Supply voltage delta, absolute value			33	V
LVCMOS Input
V_IH	High level input voltage⁽²⁾⁽⁷⁾	0.7 × V_DD			V
V_IL	Low level input voltage⁽²⁾⁽⁷⁾			0.3 × V_DD	V
Low-Speed Interface (LSIF)
f_CLOCK	LSIF clock frequency (LS_CLK)⁽⁹⁾	108	120	130	MHz
DCD_IN	LSIF duty cycle distortion (LS_CLK)	44%		56%
\| V_ID \|	LSIF differential input voltage magnitude⁽⁹⁾	150	350	440	mV
V_LVDS	LSIF voltage⁽⁹⁾	575		1520	mV
V_CM	Common mode voltage⁽⁹⁾	700	900	1300	mV
Z_LINE	Line differential impedance (PWB/trace)	90	100	110	Ω
Z_IN	Internal differential termination resistance	80	100	120	Ω
High-Speed Serial Interface (HSSI)
f_CLOCK	HSSI clock frequency (DCLK)⁽⁸⁾	1.8	1.8	1.8	GHz
DCD_IN	HSSI duty cycle distortion (DCLK)	44%	50%	56%
\| V_ID \| Data	HSSI differential input voltage magnitude Data Lane⁽⁸⁾	100	400	600	mV
\| V_ID \| CLK	HSSI differential input voltage magnitude Clock Lane⁽⁸⁾	300	400	600	mV
VCM_DC Data	Input common mode voltage (DC) Data Lane⁽⁸⁾	200	600	800	mV
VCM_DC CLK	Input common mode voltage (DC) Clk Lane⁽⁸⁾	200	600	800	mV
VCM_ACp-p	AC peak to peak (ripple) on common mode voltages of Data Lane and Clock Lane⁽⁸⁾			100	mv
Z_LINE	Line differential impedance (PWB/trace)		100		Ω
Z_IN	Internal differential termination resistance (R_Xterm)	80	100	120	Ω
Environmental
T_ARRAY	Array temperature, long-term operational⁽¹⁰⁾⁽¹¹⁾⁽¹²⁾⁽¹⁴⁾	20		30	°C
T_WINDOW	Window temperature, operational, TP2 and TP3	10		30	°C
T_{DELTA_MAX}	[maximum of TP2 or TP3] minus T_{MIN_ARRAY}⁽¹⁴⁾			5	°C
T_{DELTA_MIN}	[minimum of TP2 or TP3] minus T_{MAX_ARRAY}⁽¹⁴⁾	–10			°C
RH	Relative humidity (non-condensing)			95%
Duty Cycle	Operating Landed Duty Cycle⁽¹⁷⁾		50%
ILL_UV7	Illumination Power at wavelengths < 341nm⁽¹³⁾⁽¹⁵⁾⁽¹⁶⁾⁽¹⁹⁾			10	mW/cm²
ILL_UV6	Illumination Power at wavelengths ≥ 343nm and < 345nm⁽¹³⁾⁽¹⁵⁾⁽¹⁶⁾⁽¹⁹⁾			2.7	W/cm²
ILL_UV5	Illumination Power at wavelengths ≥ 345nm and < 355nm⁽¹³⁾⁽¹⁵⁾⁽¹⁹⁾			2.9	W/cm²
ILL_UV4	Illumination Power at wavelengths ≥ 355nm and < 365nm⁽¹³⁾⁽¹⁵⁾⁽¹⁹⁾			4.1	W/cm²
ILL_UV3	Illumination Power at wavelengths ≥ 365nm and < 385nm⁽¹³⁾⁽¹⁵⁾			5.9	W/cm²
ILL_UV2	Illumination Power at wavelengths ≥ 385nm and < 400nm⁽¹³⁾⁽¹⁵⁾			11.8	W/cm²
ILL_UV1	Illumination Power at wavelengths ≥ 400nm and < 410nm⁽¹³⁾⁽¹⁵⁾			22.5	W/cm²
ILL_UV	Illumination Power at wavelengths ≥ 365nm and < 410nm⁽¹³⁾⁽¹⁵⁾⁽¹⁸⁾			22.5	W/cm²
ILL_VIS	Illumination Power at wavelengths ≥ 410nm and < 800nm⁽¹³⁾⁽¹⁵⁾			60	W/cm²

(1) Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(2) All power supply connections are required to operate the DMD: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are required to operate the DMD.

(3) All voltage values are with respect to the V_SS ground pins.

(4) V_OFFSET supply transients must fall within the specified max voltages.

(5) To prevent excess current, the supply voltage delta | V_DDA – V_DD | must be less than the specified limit.

(6) To prevent excess current, the supply voltage delta | V_BIAS – V_OFFSET | must be less than the specified limit.

(7) The LVCMOS input pin is DMD_DEN_ARSTZ.

(8) See the high-speed serial interface (HSSI) timing requirements in the Timing Requirements.

(9) See the low-speed interface (LSIF) timing requirements in Timing Requirements.

(10) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduces device lifetime.

(11) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point (TP1) shown in DMD Thermal Test Points and the package thermal resistances using the DMD Temperature Calculation.

(12) Long-term is defined as the usable life of the device.

(13) The maximum optical power that can be incident on the DMD is limited by the maximum optical power density for each wavelength range specified and the micromirror array temperature T_ARRAY.

(14) Refer to the DMD Temperature Calculation for calculation examples.

(15) Refer to the Micromirror Power Density Calculation for calculation examples.

(16) Any 343nm or higher illumination source must use a cutoff filter to be at or below this power level by 341nm. Illumination power from 343nm down to 341nm is expected to be diminishing such that the maximum power limit at 341nm can be achieved.

(17) Landed duty cycle refers to the percentage of time an individual micromirror spends landed in one state (12.0° or –12.0°) versus the opposite state (–12.0° or 12.0°). 50% equates to a 50/50 duty cycle where the mirror has been landed 50% in the on-state and 50% in the off-state. See the Definition of Micromirror Landed-On/Landed-Off Duty Cycle for more information on Landed Duty Cycle.

(18) The total integrated illumination power density from 365nm to 410nm shall not exceed 22.5W/cm². Therefore, if 5.9W/cm² of illumination is used in the 365nm to 385nm range and 11.8W/cm² is used in the 385nm to 400nm range, then illumination in the 400nm to 410nm range must be limited to 4.8W/cm².

(19) Illumination from more than one wavelength band below 365nm may not be used simultaneously with other wavelength bands. For example, if 344nm illumination is used (≥343nm and < 345nm), another wavelength outside this band may not be used simultaneously.