DLPS269 Data sheet

DLPS269A March 2025 – June 2025 DLP991UUV

PRODUCTION DATA

5.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

PARAMETER	DESCRIPTION	MIN	MAX	UNIT
Supply Voltage
V_DD	Supply voltage for LVCMOS core logic and LVCMOS low-speed interface (LSIF)⁽¹⁾	–0.5	2.3	V
V_DDA	Supply voltage for high-speed serial interface (HSSI) receivers⁽¹⁾	–0.3	2.2	V
V_OFFSET	Supply voltage for HVCMOS and micromirror electrode⁽¹⁾⁽²⁾	–0.5	11	V
V_BIAS	Supply voltage for micromirror electrode⁽¹⁾	–0.5	19	V
V_RESET	Supply voltage for micromirror electrode⁽¹⁾	–15	0.5	V
\| V_DDA – V_DD \|	Supply voltage delta (absolute value)⁽³⁾		0.3	V
\| V_BIAS – V_OFFSET \|	Supply voltage delta (absolute value)⁽⁴⁾		11	V
\| V_BIAS – V_RESET \|	Supply voltage delta (absolute value)⁽⁵⁾		34	V
Input Voltage
	Input voltage for other inputs – LVDS and LVCMOS⁽¹⁾	–0.5	2.45	V
	Input voltage for other inputs – HSSI⁽¹⁾⁽⁶⁾	–0.2	V_DDA	V
Low speed interface (LSIF)
f_CLOCK	LSIF clock frequency (LS_CLK)		130	MHz
\| V_ID \|	LSIF differential input voltage magnitude⁽⁶⁾		810	mV
I_ID	LSIF differential input current⁽⁷⁾		10	mA
High speed serial interface (HSSI)
f_CLOCK	HSSI clock frequency (DCLK)		1.65	GHz
\| V_ID \|	HSSI differential input voltage magnitude Data Lane		700	mV
\| V_ID \|	HSSI differential input voltage magnitude Clock Lane		700	mV
Environmental
T_ARRAY	Temperature, operational⁽⁸⁾	0	90	°C
T_ARRAY	Temperature, non-operational⁽⁸⁾	–40	90	°C
T_WINDOW	Temperature, operational⁽⁸⁾	0	70	°C
T_WINDOW	Temperature, non-operational⁽⁸⁾	–40	90	°C
T_{DELTA_MAX}	[maximum of TP2 or TP3] minus T_{MIN_ARRAY}⁽⁹⁾		5	°C
T_{DELTA_MIN}	[minimum of TP2 or TP3] minus T_{MAX_ARRAY}⁽⁹⁾	–30		°C
RH	Relative humidity, operational and non-operational		95%

(1) All voltage values are with respect to the ground terminals (V_SS). The following required power supplies must be connected for proper DMD operation: V_DD, V_DDA, V_OFFSET, V_BIAS, and V_RESET. All V_SS connections are also required.

(2) V_OFFSET supply transients must fall within specified voltages.

(3) Exceeding the recommended allowable absolute voltage difference between V_DDA and V_DD can result in excessive current draw.

(4) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_OFFSET can result in excessive current draw.

(5) Exceeding the recommended allowable absolute voltage difference between V_BIAS and V_RESET can result in excessive current draw.

(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS differential inputs must not exceed the specified limit, or damage can result to the internal termination resistors.

(7) Differential inputs must not exceed the specified limit, or damage can result to the internal termination resistors. Specification applies to both the high-speed serial interface (HSSI) and the low-speed interface (LSI).

(8) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at the test point 1 (TP1) shown in Figure 6-1 and the package thermal resistances using the calculation in Section 6.6.

(9) Refer to Section 6.6 for the calculation.