DLPS289A June   2025  – September 2025 DLP391TP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     16
    11. 5.9  System Mounting Interface Loads
    12.     18
    13. 5.10 Micromirror Array Physical Characteristics
    14.     20
    15. 5.11 Micromirror Array Optical Characteristics
    16. 5.12 Window Characteristics
    17. 5.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 LPSDR Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Pin Configuration and Functions

DLP391TP FSB Package 154-Pin LGA (Bottom View)Figure 4-1 FSB Package 154-Pin LGA (Bottom View)
Table 4-1 Pin Functions
PIN(2)TYPE(1)DESCRIPTIONTERMINATIONTRACE LENGTH (mm)
NAMEPAD ID
D_AP(0)C2IHigh-Speed Differential Data Pair lane A0Differential 100Ω1.123
D_AN(0)C3IHigh-Speed Differential Data Pair lane A0Differential 100Ω1.414
D_AP(1)D2IHigh-Speed Differential Data Pair lane A1Differential 100Ω1.212
D_AN(1)D3IHigh-Speed Differential Data Pair lane A1Differential 100Ω1.626
D_AP(2)C4IHigh-Speed Differential Data Pair lane A2Differential 100Ω3.011
D_AN(2)C5IHigh-Speed Differential Data Pair lane A2Differential 100Ω3.388
D_AP(3)D5IHigh-Speed Differential Data Pair lane A3Differential 100Ω3.682
D_AN(3)D6IHigh-Speed Differential Data Pair lane A3Differential 100Ω3.912
D_AP(4)G5IHigh-Speed Differential Data Pair lane A4Differential 100Ω3.542
D_AN(4)G6IHigh-Speed Differential Data Pair lane A4Differential 100Ω3.662
D_AP(5)E2IHigh-Speed Differential Data Pair lane A5Differential 100Ω0.972
D_AN(5)E3IHigh-Speed Differential Data Pair lane A5Differential 100Ω1.335
D_AP(6)E5IHigh-Speed Differential Data Pair lane A6Differential 100Ω4.520
D_AN(6)E6IHigh-Speed Differential Data Pair lane A6Differential 100Ω4.634
D_AP(7)H5IHigh-Speed Differential Data Pair lane A7Differential 100Ω3.200
D_AN(7)H6IHigh-Speed Differential Data Pair lane A7Differential 100Ω3.515
DCLK_APF4IHigh-Speed Differential Clock ADifferential 100Ω2.610
DCLK_ANF5IHigh-Speed Differential Clock ADifferential 100Ω3.068
D_BP(0)C20IHigh-Speed Differential Data Pair lane B0Differential 100Ω2.563
D_BN(0)C19IHigh-Speed Differential Data Pair lane B0Differential 100Ω2.636
D_BP(1)D21IHigh-Speed Differential Data Pair lane B1Differential 100Ω2.329
D_BN(1)D20IHigh-Speed Differential Data Pair lane B1Differential 100Ω2.487
D_BP(2)C18IHigh-Speed Differential Data Pair lane B2Differential 100Ω4.300
D_BN(2)D18IHigh-Speed Differential Data Pair lane B2Differential 100Ω4.569
D_BP(3)E20IHigh-Speed Differential Data Pair lane B3Differential 100Ω3.112
D_BN(3)E19IHigh-Speed Differential Data Pair lane B3Differential 100Ω3.485
D_BP(4)F22IHigh-Speed Differential Data Pair lane B4Differential 100Ω1.073
D_BN(4)F21IHigh-Speed Differential Data Pair lane B4Differential 100Ω1.239
D_BP(5)H18IHigh-Speed Differential Data Pair lane B5Differential 100Ω4.146
D_BN(5)G18IHigh-Speed Differential Data Pair lane B5Differential 100Ω4.330
D_BP(6)F18IHigh-Speed Differential Data Pair lane B6Differential 100Ω4.241
D_BN(6)E18IHigh-Speed Differential Data Pair lane B6Differential 100Ω4.494
D_BP(7)G22IHigh-Speed Differential Data Pair lane B7Differential 100Ω0.663
D_BN(7)G21IHigh-Speed Differential Data Pair lane B7Differential 100Ω1.054
DCLK_BPF20IHigh-Speed Differential Clock BDifferential 100Ω2.404
DCLK_BNF19IHigh-Speed Differential Clock BDifferential 100Ω2.610
D_CP(0)G2IHigh-Speed Differential Data Pair lane C0Differential 100Ω1.052
D_CN(0)G3IHigh-Speed Differential Data Pair lane C0Differential 100Ω1.112
D_CP(1)M7IHigh-Speed Differential Data Pair lane C1Differential 100Ω6.519
D_CN(1)M8IHigh-Speed Differential Data Pair lane C1Differential 100Ω6.611
D_CP(2)H2IHigh-Speed Differential Data Pair lane C2Differential 100Ω0.921
D_CN(2)H3IHigh-Speed Differential Data Pair lane C2Differential 100Ω1.376
D_CP(3)M5IHigh-Speed Differential Data Pair lane C3Differential 100Ω5.196
D_CN(3)M6IHigh-Speed Differential Data Pair lane C3Differential 100Ω5.318
D_CP(4)K3IHigh-Speed Differential Data Pair lane C4Differential 100Ω1.579
D_CN(4)K4IHigh-Speed Differential Data Pair lane C4Differential 100Ω1.648
D_CP(5)M3IHigh-Speed Differential Data Pair lane C5Differential 100Ω3.414
D_CN(5)M4IHigh-Speed Differential Data Pair lane C5Differential 100Ω3.857
D_CP(6)L4IHigh-Speed Differential Data Pair lane C6Differential 100Ω2.460
D_CN(6)L5IHigh-Speed Differential Data Pair lane C6Differential 100Ω2.566
D_CP(7)K1IHigh-Speed Differential Data Pair lane C7Differential 100Ω1.114
D_CN(7)L1IHigh-Speed Differential Data Pair lane C7Differential 100Ω1.707
DCLK_CPK5IHigh-Speed Differential Clock CDifferential 100Ω3.744
DCLK_CNK6IHigh-Speed Differential Clock CDifferential 100Ω3.883
D_DP(0)J19IHigh-Speed Differential Data Pair lane D0Differential 100Ω4.189
D_DN(0)J18IHigh-Speed Differential Data Pair lane D0Differential 100Ω4.435
D_DP(1)M18IHigh-Speed Differential Data Pair lane D1Differential 100Ω6.588
D_DN(1)M17IHigh-Speed Differential Data Pair lane D1Differential 100Ω6.867
D_DP(2)H21IHigh-Speed Differential Data Pair lane D2Differential 100Ω1.754
D_DN(2)H20IHigh-Speed Differential Data Pair lane D2Differential 100Ω1.936
D_DP(3)J22IHigh-Speed Differential Data Pair lane D3Differential 100Ω1.339
D_DN(3)J21IHigh-Speed Differential Data Pair lane D3Differential 100Ω1.634
D_DP(4)L20IHigh-Speed Differential Data Pair lane D4Differential 100Ω3.329
D_DN(4)L19IHigh-Speed Differential Data Pair lane D4Differential 100Ω3.436
D_DP(5)M20IHigh-Speed Differential Data Pair lane D5Differential 100Ω3.631
D_DN(5)M19IHigh-Speed Differential Data Pair lane D5Differential 100Ω3.738
D_DP(6)M22IHigh-Speed Differential Data Pair lane D6Differential 100Ω2.420
D_DN(6)M21IHigh-Speed Differential Data Pair lane D6Differential 100Ω2.573
D_DP(7)K22IHigh-Speed Differential Data Pair lane D7Differential 100Ω1.406
D_DN(7)K21IHigh-Speed Differential Data Pair lane D7Differential 100Ω1.881
DCLK_DPK19IHigh-Speed Differential Clock DDifferential 100Ω3.916
DCLK_DNK18IHigh-Speed Differential Clock DDifferential 100Ω4.022
TEMP_NM2ITemp Diode N1.133
TEMP_PM1ITemp Diode P1.237
LS_RDATA_DB7OLPSDR Output4.978
LS_RDATA_CA4OLPSDR Output2.897
LS_WDATAB5ILPSDR Input2.524
LS_RDATA_BA7OLPSDR Output5.103
LS_RDATA_AA3OLPSDR Output1.725
LS_CLKA5ILPSDR Input2.454
DMD_DEN_ARSTZD1IARSTZ17.5kΩ pulldown0.735
VDDA6, A8, A10, A12, A14, A16, A18, B4, B11, B13, B15, B19, B21, C21, D22, E21, G4, J1, J4, J6, L2, M15PDigital Core Supply Voltage8.350
VBIASA20, B6PSupply Voltage for Positive Bias of Micromirror reset signal7.409
VRESETB8, B17PSupply Voltage for Negative Bias of Micromirror reset signal3.374
VOFFSETB9, M16PSupply voltage for HVCMOS logic,stepped up logic level1.797
VDDIC22, E4, F2, G20, J2,L22P19.977
VSSA9, A11, A13, A15, A17, A19, B3, B10, B12, B14, B16, B18, B20, C1, C6, D4, D19, E22, F3, F6, G19, H4, H19, H22, J3, J5, J20, K2, K20, L3, L6, L18, L21, M9GGround12.614
N/CA21, C23, K23, L23, M23NCNo Connect PinN/A
I=Input, O=Output, P=Power, G=Ground, NC=No Connect
Only 151 pins are electrically connected for functional use.