DLPS289A June 2025 – September 2025 DLP391TP
PRODUCTION DATA
Figure 4-1 FSB Package 154-Pin LGA (Bottom View)| PIN(2) | TYPE(1) | DESCRIPTION | TERMINATION | TRACE LENGTH (mm) | |
|---|---|---|---|---|---|
| NAME | PAD ID | ||||
| D_AP(0) | C2 | I | High-Speed Differential Data Pair lane A0 | Differential 100Ω | 1.123 |
| D_AN(0) | C3 | I | High-Speed Differential Data Pair lane A0 | Differential 100Ω | 1.414 |
| D_AP(1) | D2 | I | High-Speed Differential Data Pair lane A1 | Differential 100Ω | 1.212 |
| D_AN(1) | D3 | I | High-Speed Differential Data Pair lane A1 | Differential 100Ω | 1.626 |
| D_AP(2) | C4 | I | High-Speed Differential Data Pair lane A2 | Differential 100Ω | 3.011 |
| D_AN(2) | C5 | I | High-Speed Differential Data Pair lane A2 | Differential 100Ω | 3.388 |
| D_AP(3) | D5 | I | High-Speed Differential Data Pair lane A3 | Differential 100Ω | 3.682 |
| D_AN(3) | D6 | I | High-Speed Differential Data Pair lane A3 | Differential 100Ω | 3.912 |
| D_AP(4) | G5 | I | High-Speed Differential Data Pair lane A4 | Differential 100Ω | 3.542 |
| D_AN(4) | G6 | I | High-Speed Differential Data Pair lane A4 | Differential 100Ω | 3.662 |
| D_AP(5) | E2 | I | High-Speed Differential Data Pair lane A5 | Differential 100Ω | 0.972 |
| D_AN(5) | E3 | I | High-Speed Differential Data Pair lane A5 | Differential 100Ω | 1.335 |
| D_AP(6) | E5 | I | High-Speed Differential Data Pair lane A6 | Differential 100Ω | 4.520 |
| D_AN(6) | E6 | I | High-Speed Differential Data Pair lane A6 | Differential 100Ω | 4.634 |
| D_AP(7) | H5 | I | High-Speed Differential Data Pair lane A7 | Differential 100Ω | 3.200 |
| D_AN(7) | H6 | I | High-Speed Differential Data Pair lane A7 | Differential 100Ω | 3.515 |
| DCLK_AP | F4 | I | High-Speed Differential Clock A | Differential 100Ω | 2.610 |
| DCLK_AN | F5 | I | High-Speed Differential Clock A | Differential 100Ω | 3.068 |
| D_BP(0) | C20 | I | High-Speed Differential Data Pair lane B0 | Differential 100Ω | 2.563 |
| D_BN(0) | C19 | I | High-Speed Differential Data Pair lane B0 | Differential 100Ω | 2.636 |
| D_BP(1) | D21 | I | High-Speed Differential Data Pair lane B1 | Differential 100Ω | 2.329 |
| D_BN(1) | D20 | I | High-Speed Differential Data Pair lane B1 | Differential 100Ω | 2.487 |
| D_BP(2) | C18 | I | High-Speed Differential Data Pair lane B2 | Differential 100Ω | 4.300 |
| D_BN(2) | D18 | I | High-Speed Differential Data Pair lane B2 | Differential 100Ω | 4.569 |
| D_BP(3) | E20 | I | High-Speed Differential Data Pair lane B3 | Differential 100Ω | 3.112 |
| D_BN(3) | E19 | I | High-Speed Differential Data Pair lane B3 | Differential 100Ω | 3.485 |
| D_BP(4) | F22 | I | High-Speed Differential Data Pair lane B4 | Differential 100Ω | 1.073 |
| D_BN(4) | F21 | I | High-Speed Differential Data Pair lane B4 | Differential 100Ω | 1.239 |
| D_BP(5) | H18 | I | High-Speed Differential Data Pair lane B5 | Differential 100Ω | 4.146 |
| D_BN(5) | G18 | I | High-Speed Differential Data Pair lane B5 | Differential 100Ω | 4.330 |
| D_BP(6) | F18 | I | High-Speed Differential Data Pair lane B6 | Differential 100Ω | 4.241 |
| D_BN(6) | E18 | I | High-Speed Differential Data Pair lane B6 | Differential 100Ω | 4.494 |
| D_BP(7) | G22 | I | High-Speed Differential Data Pair lane B7 | Differential 100Ω | 0.663 |
| D_BN(7) | G21 | I | High-Speed Differential Data Pair lane B7 | Differential 100Ω | 1.054 |
| DCLK_BP | F20 | I | High-Speed Differential Clock B | Differential 100Ω | 2.404 |
| DCLK_BN | F19 | I | High-Speed Differential Clock B | Differential 100Ω | 2.610 |
| D_CP(0) | G2 | I | High-Speed Differential Data Pair lane C0 | Differential 100Ω | 1.052 |
| D_CN(0) | G3 | I | High-Speed Differential Data Pair lane C0 | Differential 100Ω | 1.112 |
| D_CP(1) | M7 | I | High-Speed Differential Data Pair lane C1 | Differential 100Ω | 6.519 |
| D_CN(1) | M8 | I | High-Speed Differential Data Pair lane C1 | Differential 100Ω | 6.611 |
| D_CP(2) | H2 | I | High-Speed Differential Data Pair lane C2 | Differential 100Ω | 0.921 |
| D_CN(2) | H3 | I | High-Speed Differential Data Pair lane C2 | Differential 100Ω | 1.376 |
| D_CP(3) | M5 | I | High-Speed Differential Data Pair lane C3 | Differential 100Ω | 5.196 |
| D_CN(3) | M6 | I | High-Speed Differential Data Pair lane C3 | Differential 100Ω | 5.318 |
| D_CP(4) | K3 | I | High-Speed Differential Data Pair lane C4 | Differential 100Ω | 1.579 |
| D_CN(4) | K4 | I | High-Speed Differential Data Pair lane C4 | Differential 100Ω | 1.648 |
| D_CP(5) | M3 | I | High-Speed Differential Data Pair lane C5 | Differential 100Ω | 3.414 |
| D_CN(5) | M4 | I | High-Speed Differential Data Pair lane C5 | Differential 100Ω | 3.857 |
| D_CP(6) | L4 | I | High-Speed Differential Data Pair lane C6 | Differential 100Ω | 2.460 |
| D_CN(6) | L5 | I | High-Speed Differential Data Pair lane C6 | Differential 100Ω | 2.566 |
| D_CP(7) | K1 | I | High-Speed Differential Data Pair lane C7 | Differential 100Ω | 1.114 |
| D_CN(7) | L1 | I | High-Speed Differential Data Pair lane C7 | Differential 100Ω | 1.707 |
| DCLK_CP | K5 | I | High-Speed Differential Clock C | Differential 100Ω | 3.744 |
| DCLK_CN | K6 | I | High-Speed Differential Clock C | Differential 100Ω | 3.883 |
| D_DP(0) | J19 | I | High-Speed Differential Data Pair lane D0 | Differential 100Ω | 4.189 |
| D_DN(0) | J18 | I | High-Speed Differential Data Pair lane D0 | Differential 100Ω | 4.435 |
| D_DP(1) | M18 | I | High-Speed Differential Data Pair lane D1 | Differential 100Ω | 6.588 |
| D_DN(1) | M17 | I | High-Speed Differential Data Pair lane D1 | Differential 100Ω | 6.867 |
| D_DP(2) | H21 | I | High-Speed Differential Data Pair lane D2 | Differential 100Ω | 1.754 |
| D_DN(2) | H20 | I | High-Speed Differential Data Pair lane D2 | Differential 100Ω | 1.936 |
| D_DP(3) | J22 | I | High-Speed Differential Data Pair lane D3 | Differential 100Ω | 1.339 |
| D_DN(3) | J21 | I | High-Speed Differential Data Pair lane D3 | Differential 100Ω | 1.634 |
| D_DP(4) | L20 | I | High-Speed Differential Data Pair lane D4 | Differential 100Ω | 3.329 |
| D_DN(4) | L19 | I | High-Speed Differential Data Pair lane D4 | Differential 100Ω | 3.436 |
| D_DP(5) | M20 | I | High-Speed Differential Data Pair lane D5 | Differential 100Ω | 3.631 |
| D_DN(5) | M19 | I | High-Speed Differential Data Pair lane D5 | Differential 100Ω | 3.738 |
| D_DP(6) | M22 | I | High-Speed Differential Data Pair lane D6 | Differential 100Ω | 2.420 |
| D_DN(6) | M21 | I | High-Speed Differential Data Pair lane D6 | Differential 100Ω | 2.573 |
| D_DP(7) | K22 | I | High-Speed Differential Data Pair lane D7 | Differential 100Ω | 1.406 |
| D_DN(7) | K21 | I | High-Speed Differential Data Pair lane D7 | Differential 100Ω | 1.881 |
| DCLK_DP | K19 | I | High-Speed Differential Clock D | Differential 100Ω | 3.916 |
| DCLK_DN | K18 | I | High-Speed Differential Clock D | Differential 100Ω | 4.022 |
| TEMP_N | M2 | I | Temp Diode N | 1.133 | |
| TEMP_P | M1 | I | Temp Diode P | 1.237 | |
| LS_RDATA_D | B7 | O | LPSDR Output | 4.978 | |
| LS_RDATA_C | A4 | O | LPSDR Output | 2.897 | |
| LS_WDATA | B5 | I | LPSDR Input | 2.524 | |
| LS_RDATA_B | A7 | O | LPSDR Output | 5.103 | |
| LS_RDATA_A | A3 | O | LPSDR Output | 1.725 | |
| LS_CLK | A5 | I | LPSDR Input | 2.454 | |
| DMD_DEN_ARSTZ | D1 | I | ARSTZ | 17.5kΩ pulldown | 0.735 |
| VDD | A6, A8, A10, A12, A14, A16, A18, B4, B11, B13, B15, B19, B21, C21, D22, E21, G4, J1, J4, J6, L2, M15 | P | Digital Core Supply Voltage | 8.350 | |
| VBIAS | A20, B6 | P | Supply Voltage for Positive Bias of Micromirror reset signal | 7.409 | |
| VRESET | B8, B17 | P | Supply Voltage for Negative Bias of Micromirror reset signal | 3.374 | |
| VOFFSET | B9, M16 | P | Supply voltage for HVCMOS logic,stepped up logic level | 1.797 | |
| VDDI | C22, E4, F2, G20, J2,L22 | P | 19.977 | ||
| VSS | A9, A11, A13, A15, A17, A19, B3, B10, B12, B14, B16, B18, B20, C1, C6, D4, D19, E22, F3, F6, G19, H4, H19, H22, J3, J5, J20, K2, K20, L3, L6, L18, L21, M9 | G | Ground | 12.614 | |
| N/C | A21, C23, K23, L23, M23 | NC | No Connect Pin | N/A | |