DLPS289A June   2025  – September 2025 DLP391TP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6. 5.5  Thermal Information
    7. 5.6  Electrical Characteristics
    8. 5.7  Switching Characteristics
    9. 5.8  Timing Requirements
    10.     16
    11. 5.9  System Mounting Interface Loads
    12.     18
    13. 5.10 Micromirror Array Physical Characteristics
    14.     20
    15. 5.11 Micromirror Array Optical Characteristics
    16. 5.12 Window Characteristics
    17. 5.13 Chipset Component Usage Specification
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 LPSDR Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. Layout
    1. 9.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Device Support
      1. 10.2.1 Device Nomenclature
      2. 10.2.2 Device Markings
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER (6)TEST CONDITIONS (2)MINTYPMAXUNIT
CURRENT
IDDSupply current: VDD (3)(4)Typical140mA
IDDISupply current: VDDI (3)(4)Typical45mA
IOFFSETSupply current: VOFFSET (5)Typical6mA
IBIASSupply current: VBIAS (5)Typical0.6mA
IRESETSupply current: VRESETTypical1.8mA
POWER
PDDSupply power dissipation: VDD (3)(4)Typical252mW
PDDISupply power dissipation: VDDI (3)(4)Typical81mW
POFFSETSupply power dissipation: VOFFSET (5)Typical60mW
PBIASSupply power dissipation: VBIAS (5)Typical1.08mW
PRESETSupply power dissipation: VRESETTypical25.2mW
PTOTALSupply power dissipation TotalTypical419.28mW
LPSDR INPUT
IILLow level input currentVDD = 1.95V, VI = 0V-100nA
IIHHigh level input currentVDD = 1.95V, VI = 1.95V135uA
LPSDR OUTPUT
VOHDC output high voltage (7)(8)(9)IOH = -2mA0.8 x VDDV
VOLDC output low voltage (7)(8)(9)IOL = 2mA0.2 x VDDV
CAPACITANCE
CINInput capacitance LVCMOSF = 1MHz10pF
CINInput capacitance SubLVDSF = 1MHz20pF
COUTOutput capacitanceF = 1MHz10pF
CTEMPTemperature sense diode capacitanceF = 1MHz20pF
Device electrical characteristics are over Section 5.4 unless otherwise noted.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta | VDDI – VDD | must be less than the specified limit.
Supply power dissipation based on non–compressed commands and data.
To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than the specified limit.
All power supply connections are required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also
required.
LPSDR specifications are for pins LS_CLK and LS_WDATA.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC
Standard No. 209-2F, Low-Power Double Data Rate (LPDDR) JESD209-2F.
LPSDR output specification is for pins LS_RDATA_A, LS_RDATA_B, LS_RDATA_C, LS_RDATA_D.