DLPS289 Data sheet

DLPS289A June 2025 – September 2025 DLP391TP

PRODUCTION DATA

5.8 Timing Requirements

Over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
LVCMOS
LPSDR
t_r	Rise slew rate ⁽²⁾	(20% to 80%) × VDD⁽⁶⁾	0.25			V/ns
t_f	Fall slew rate ⁽²⁾	(80% to 20%) × VDD⁽⁶⁾	0.25			V/ns
t_r	Rise slew rate ⁽¹⁾	(30% to 80%) × VDD⁽⁶⁾	1		3	V/ns
t_f	Fall slew rate ⁽¹⁾	(70% to 20%) × VDD⁽⁶⁾	1		3	V/ns
t_W(H)	Pulse duration LS_CLK high	50% to 50% reference points⁽⁵⁾	4.2			ns
t_W(L)	Pulse duration LS_CLK low	50% to 50% reference points⁽⁵⁾	4.2			ns
t_su	Setup time	LS_WDATA valid before LS_CLK⁽⁵⁾			1.5	ns
t_h	Hold time	LS_WDATA valid after LS_CLK⁽⁵⁾			1.5	ns
SubLVDS
t_r	Rise slew rate	20% to 80% reference points⁽⁷⁾	0.7	1		V/ns
t_f	Fall slew rate	80% to 20% reference points⁽⁷⁾	0.7	1		V/ns
t_W(H)	Pulse duration DCLK high	50% to 50% reference points⁽⁸⁾	0.7			ns
t_W(L)	Pulse duration DCLK low	50% to 50% reference points⁽⁸⁾	0.7			ns
t_WINDOW	Window time ⁽¹⁾⁽³⁾	Setup time + Hold time⁽⁵⁾	0.25			ns
t_su	Setup time	HS_DATA valid before HS_CLK⁽⁸⁾			0.17	ns
t_h	Hold time	HS_DATA valid after HS_CLK⁽⁸⁾			0.17	ns
t_POWER	Power-up receiver⁽⁴⁾				200	ns

(1) The specification is for the DMD_DEN_ARSTZ pin. Refer to the LPSDR input rise and fall slew rate in Figure 5-4.

(2) The specification is for the LS_CLK and LS_WDATA pins. Refer to the LPSDR input rise and fall slew rate in Figure 5-4.

(3) Window time derating example: 0.5V/ns slew rate increases the window time by 0.7ns, from 3ns to 3.7ns. See Figure 5-6.

(4) The specification is for the SubLVDS receiver time only and does not take into account commanding and latency after commanding.