DLPU113A December   2021  – April 2022 DLP2021-Q1

 

  1.   Trademarks
  2. 1DLP2021-Q1 Electronics EVM Overview
    1. 1.1 Introduction
    2. 1.2 What is in the DLP2021-Q1 Light Engine EVM
      1. 1.2.1 Formatter Subsystem
      2. 1.2.2 Illumination Subsystem
      3. 1.2.3 Light Engine
      4. 1.2.4 Cables
    3. 1.3 Non-Optical Specifications
      1. 1.3.1 Electrical Specifications
      2. 1.3.2 Component Temperature Ratings
      3. 1.3.3 LED Driver Design
      4. 1.3.4 Video Specification
  3. 2Quick Start
    1. 2.1 Kit Assembly Instructions
    2. 2.2 Software Installation
    3. 2.3 Power-Up
    4. 2.4 Select Display Content
    5. 2.5 LED Driver
  4. 3Optics and Mechanics
  5. 4Software
    1. 4.1 DLP Composer
      1. 4.1.1 Default Register Configuration
      2. 4.1.2 Illumination
      3. 4.1.3 Sequence Set
      4. 4.1.4 Degamma Curves
      5. 4.1.5 Image/Video
      6. 4.1.6 Flash Blocks
      7. 4.1.7 Flash Programming
    2. 4.2 DLP Control Program
      1. 4.2.1 Connection
      2. 4.2.2 Scripting
      3. 4.2.3 Registers
      4. 4.2.4 Commands
    3. 4.3 MSP430 Example Code
  6. 5Revision History

4.3 MSP430 Example Code

When power is applied to the system, the FPGA configuration is loaded to the FPGA. Depending on the default configuration, the FPGA begins loading bit-planes to the DMD and sequencing the LED enables for each bit plane loaded. Alternatively, a microcontroller such as the MSP430G2553-Q1 on the EVM, can issue commands to the FPGA via SPI to enable video playback, change videos, read DMD temperature via the TMP411, or adjust current levels to the LEDs. The MSP430 Example Code (DLPC138) is a Code Composer Studio example project available for users to edit and refer to for a custom Local Host Control operation mode implementation.

GUID-1B598A2E-86AC-422A-8314-0C6040542032-low.pngFigure 4-15 MSP430G2553-Q1 Code Composer Example Project for DGP EVM