SBAA661 February   2025 LMX1205

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Flicker Noise, Noise Floor, and Total Noise
    1. 1.1 Flicker Noise
    2. 1.2 Noise Floor
    3. 1.3 Total Noise
  5. 2Finding the Slew Rate
    1. 2.1 Finding the Slew Rate With an Oscilloscope
    2. 2.2 Calculating the Slew Rate From Power and Frequency
  6. 3Impact of Slew Rate on Phase Noise
    1. 3.1 Modeling of Input Clock Slew Rate, Inherent Device Noise, and Output Jitter
    2. 3.2 Slew Rate Impact on Flicker Noise and Noise Floor
  7. 4Application of Slew Rate Rules to PLL Synthesizers
    1. 4.1 PLL Flicker Noise
    2. 4.2 PLL Figure of Merit
    3. 4.3 Other Areas in PLLs Where Slew Rate has an Impact on Performance
    4. 4.4 Improving PLL Slew Rate for Better Performance
  8. 5Application of Slew Rate Rules to Data Converters
  9. 6Summary
  10. 7References
  11.   Appendix A: Relating Slew Rate, Power, and Frequency
  12.   Appendix B: Relating Slew Rate, Frequency, Jitter, and Phase Noise
  13.   Appendix C: Equations for Data Converters
    1. 8.1 Relating Sampled Signal Slew Rate to SNR
    2. 8.2 Justification That SNR Decreases 1dB per 1dB With Input Power for Slew Rate Limited Case
  14.   Appendix D: Calculations for Data Converter Example

4.2 PLL Figure of Merit

For the noise floor, PLLs often characterize this in terms of figure of merit (FOM). This is a useful metric as the metric allows one to characterize the PLL noise floor with a single number. The noise floor can be calculated from the PLL figure of merit using feedback divider value (N) and phase detector frequency (fPD).

Equation 19. P N   N o i s e   F l o o r = F O M + 20 × log ⁡ N + 10 × log ⁡ f P D

Figure 4-2 shows the impact of input power on the PLL figure of merit

Impact of Clock Input Power for PLL Figure of Merit for LMX2615-SP PLL Figure 4-2 Impact of Clock Input Power for PLL Figure of Merit for LMX2615-SP PLL

Not shown is the impact of using a constant input power, but changing the input frequency. For a PLL, the R divider can divide the input clock frequency down and in doing so, phase noise is improved. When changing the input frequency and dividing the frequency down, this also divides down the internal buffer input noise as well. So in many cases, doubling the input clock frequency and doubling the R divider can improve the phase noise of a PLL.