SBAA661 February 2025 LMX1205
Understanding the impact of slew rate on phase noise starts with modeling this on a simple buffer as shown in Figure 3-1. This understanding can then be expanded to understand the impact of input clock slew rate for PLLs, data converters, and clock buffers because they all contain an input buffer. The noise modeling starts with the assumption that the input clock has no noise and has some known slew rate. The inherent device noise can be modeled as an rms voltage that adds to the input clock to create an internal resultant signal. The signal then goes through a comparator that squares it up to produce the output signal.