SBAA661 February   2025 LMX1205

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Flicker Noise, Noise Floor, and Total Noise
    1. 1.1 Flicker Noise
    2. 1.2 Noise Floor
    3. 1.3 Total Noise
  5. 2Finding the Slew Rate
    1. 2.1 Finding the Slew Rate With an Oscilloscope
    2. 2.2 Calculating the Slew Rate From Power and Frequency
  6. 3Impact of Slew Rate on Phase Noise
    1. 3.1 Modeling of Input Clock Slew Rate, Inherent Device Noise, and Output Jitter
    2. 3.2 Slew Rate Impact on Flicker Noise and Noise Floor
  7. 4Application of Slew Rate Rules to PLL Synthesizers
    1. 4.1 PLL Flicker Noise
    2. 4.2 PLL Figure of Merit
    3. 4.3 Other Areas in PLLs Where Slew Rate has an Impact on Performance
    4. 4.4 Improving PLL Slew Rate for Better Performance
  8. 5Application of Slew Rate Rules to Data Converters
  9. 6Summary
  10. 7References
  11.   Appendix A: Relating Slew Rate, Power, and Frequency
  12.   Appendix B: Relating Slew Rate, Frequency, Jitter, and Phase Noise
  13.   Appendix C: Equations for Data Converters
    1. 8.1 Relating Sampled Signal Slew Rate to SNR
    2. 8.2 Justification That SNR Decreases 1dB per 1dB With Input Power for Slew Rate Limited Case
  14.   Appendix D: Calculations for Data Converter Example

8.2 Justification That SNR Decreases 1dB per 1dB With Input Power for Slew Rate Limited Case

Start with the assumption that the clock jitter dominates and the slew rate limited. Table 3-1 shows that the phase noise is related to 20×log(SR). Equation 5 shows that a 6dB increase in clock power doubles the slew rate. Equation 33 relates phase noise to jitter. So therefore a 6dB increase in input power improves the phase noise by 6dB. This in turn reduces the jitter by a factor of 2. Equation 47 shows that this leads to a 6dB improvement in SNR. So to generalize this rule for a slew rate limited SNR for a data converter.

Equation 48. S N R ∝ C l o c k   I n p u t   P o w e r