Input clock slew rate can impact PLL fractional spurs. The reason for this is that is fractional spur energy from the fractional circuitry can couple to the input path of the PLL. This behaves in a very similar way as the inherent device noise in Figure 3-1. The resulting jitter is multiplied by 20×log(N). In the case where the input clock slew rate is low enough for the spur to be slew rate limited, increasing the input power by 1dB can improve the spur by 1dB. However, increasing the clock slew rate too much creates a stronger signal on the input and this can couple and mix. So for this reason, a high slew rate, but low frequency input, like LVDS, is designed for PLL spurs.

Slew rate also impact PLL R and N divider sensitivity. Sensitivity is the minimum power required for the counter to correctly function and where the output frequency is measured to be within 1Hz of the value needing to be. The inputs to these counters have an internal voltage noise and therefore sensitivity curves often have the bowl shape as shown for the noise floor as in Figure 2-1.