SBAS501D May   2013  – May 2026 ADS1220

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 Bypassing the PGA
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Clock Source
      5. 8.3.5  Modulator
      6. 8.3.6  Digital Filter
      7. 8.3.7  Output Data Rate
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Low-Side Power Switch
      10. 8.3.10 Sensor Detection
      11. 8.3.11 System Monitor
      12. 8.3.12 Offset Calibration
      13. 8.3.13 Temperature Sensor
        1. 8.3.13.1 Converting From Digital Codes to Temperature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Single-Shot Conversion Mode
        2. 8.4.2.2 Continuous Conversion Mode
      3. 8.4.3 Operating Modes
        1. 8.4.3.1 Normal Mode
        2. 8.4.3.2 Duty-Cycle Mode
        3. 8.4.3.3 Turbo Mode
        4. 8.4.3.4 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready ( DRDY)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Timeout
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 RESET (0000 011xb)
        2. 8.5.3.2 START/SYNC (0000 100xb)
        3. 8.5.3.3 POWERDOWN (0000 001xb)
        4. 8.5.3.4 RDATA (0001 xxxxb)
        5. 8.5.3.5 RREG (0010 rrnnb)
        6. 8.5.3.6 WREG (0100 rrnnb)
      4. 8.5.4 Reading Data
      5. 8.5.5 Sending Commands
      6. 8.5.6 Interfacing with Multiple Devices
    6. 8.6 Register Map
      1. 8.6.1 Configuration Registers
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1 Configuration Register 0 (Address = 00h) [reset = 00h]
        2. 8.6.2.2 Configuration Register 1 (Address = 01h) [reset = 00h]
        3. 8.6.2.3 Configuration Register 2 (Address = 02h) [reset = 00h]
        4. 8.6.2.4 Configuration Register 3 (Address = 03h) [reset = 00h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Unused Inputs and Outputs
      6. 9.1.6 Pseudo Code Example
    2. 9.2 Typical Applications
      1. 9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Resistive Bridge Measurement
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Ramp Rate
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.6 Digital Filter

The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the different data rates and always settles within a single cycle. At data rates of 5SPS and 20SPS, use the 50/60[1:0] bits in the configuration register to select line frequency rejections of 50Hz or 60Hz or to simultaneously reject 50Hz and 60Hz. The frequency responses of the digital filter are illustrated in Figure 8-9 to Figure 8-22 for different output data rates using the internal oscillator or an external 4.096MHz clock.

The filter notches and output data rate scale proportionally with the clock frequency. For example, a notch that appears at 20Hz when using a 4.096MHz clock appears at 10Hz if a 2.048MHz clock is used. The internal oscillator can vary over temperature as specified in the Electrical Characteristics table. The data rate or conversion time, respectively, and filter notches consequently vary by the same amount. Consider using an external precision clock source if a digital filter notch at a specific frequency with a tighter tolerance is required.

ADS1220 Filter Response (DR = 20SPS)
Simultaneous 50Hz and 60Hz Rejection, 50/60[1:0] = 01b
Figure 8-9 Filter Response
(DR = 20SPS)
ADS1220 Detailed View of Filter Response (DR = 20SPS)
Simultaneous 50Hz and 60Hz Rejection, 50/60[1:0] = 01b
Figure 8-10 Detailed View of Filter Response
(DR = 20SPS)
ADS1220 Filter Response (DR = 20SPS)
50Hz Rejection Only, 50/60[1:0] = 10b
Figure 8-11 Filter Response
(DR = 20SPS)
ADS1220 Filter Response (DR = 20SPS)
60Hz Rejection Only, 50/60[1:0] = 11b
Figure 8-13 Filter Response
(DR = 20SPS)
ADS1220 Filter Response (DR = 20SPS)
50/60[1:0] = 00b
Figure 8-15 Filter Response
(DR = 20SPS)
ADS1220 Filter Response (DR = 90SPS)
Figure 8-17 Filter Response
(DR = 90SPS)
ADS1220 Filter Response (DR = 330SPS)
Figure 8-19 Filter Response
(DR = 330SPS)
ADS1220 Filter Response (DR = 1kSPS)
Figure 8-21 Filter Response
(DR = 1kSPS)
ADS1220 Detailed View of Filter Response (DR = 20SPS)
50Hz Rejection Only, 50/60[1:0] = 10b
Figure 8-12 Detailed View of Filter Response
(DR = 20SPS)
ADS1220 Detailed View of Filter Response (DR = 20SPS)
60Hz Rejection Only, 50/60[1:0] = 11b
Figure 8-14 Detailed View of Filter Response
(DR = 20SPS)
ADS1220 Filter Response (DR = 45SPS)
 
Figure 8-16 Filter Response
(DR = 45SPS)
ADS1220 Filter Response (DR = 175SPS)
Figure 8-18 Filter Response
(DR = 175SPS)
ADS1220 Filter Response (DR = 600SPS)
Figure 8-20 Filter Response
(DR = 600SPS)
ADS1220 Filter Response (DR = 2kSPS)
Figure 8-22 Filter Response
(DR = 2kSPS)