SBAS501D May   2013  – May 2026 ADS1220

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 Bypassing the PGA
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Clock Source
      5. 8.3.5  Modulator
      6. 8.3.6  Digital Filter
      7. 8.3.7  Output Data Rate
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Low-Side Power Switch
      10. 8.3.10 Sensor Detection
      11. 8.3.11 System Monitor
      12. 8.3.12 Offset Calibration
      13. 8.3.13 Temperature Sensor
        1. 8.3.13.1 Converting From Digital Codes to Temperature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Single-Shot Conversion Mode
        2. 8.4.2.2 Continuous Conversion Mode
      3. 8.4.3 Operating Modes
        1. 8.4.3.1 Normal Mode
        2. 8.4.3.2 Duty-Cycle Mode
        3. 8.4.3.3 Turbo Mode
        4. 8.4.3.4 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready ( DRDY)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Timeout
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 RESET (0000 011xb)
        2. 8.5.3.2 START/SYNC (0000 100xb)
        3. 8.5.3.3 POWERDOWN (0000 001xb)
        4. 8.5.3.4 RDATA (0001 xxxxb)
        5. 8.5.3.5 RREG (0010 rrnnb)
        6. 8.5.3.6 WREG (0100 rrnnb)
      4. 8.5.4 Reading Data
      5. 8.5.5 Sending Commands
      6. 8.5.6 Interfacing with Multiple Devices
    6. 8.6 Register Map
      1. 8.6.1 Configuration Registers
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1 Configuration Register 0 (Address = 00h) [reset = 00h]
        2. 8.6.2.2 Configuration Register 1 (Address = 01h) [reset = 00h]
        3. 8.6.2.3 Configuration Register 2 (Address = 02h) [reset = 00h]
        4. 8.6.2.4 Configuration Register 3 (Address = 03h) [reset = 00h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Unused Inputs and Outputs
      6. 9.1.6 Pseudo Code Example
    2. 9.2 Typical Applications
      1. 9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Resistive Bridge Measurement
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Ramp Rate
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

9.2.3.2 Detailed Design Procedure

To implement a ratiometric bridge measurement, the bridge excitation voltage is simultaneously used as the reference voltage for the ADC, as shown in Figure 9-11. With this configuration, any drift in excitation voltage also shows up on the reference voltage, consequently canceling out drift error. Either of the two device reference input pairs can be connected to the bridge excitation voltage. However, only the negative reference input (REFN1) can be internally routed to a low-side power switch. By connecting the low side of the bridge to REFN1, the device can automatically power-down the bridge by opening the low-side power switch. When the PSW bit in the configuration register is set to 1b, the device opens the switch every time a POWERDOWN command is issued and closes the switch again when a START/SYNC command is sent.

The PGA offers gains up to 128, which helps amplify the small differential bridge output signal to make optimal use of the ADC full-scale range. The output signal of the bridge meets the common-mode voltage requirement of the PGA when a symmetrical bridge is used with the excitation voltage equal to the supply voltage of the device.

The maximum input voltage of ADS1220 is limited to VIN (MAX) = ±[(AVDD – AVSS) – 0.4V] / Gain, which means the entire full-scale range, FSR = ±(AVDD – AVSS) / Gain, cannot be used in this configuration. This limitation is a result of the output drive capability of the PGA amplifiers (A1 and A2); see Figure 8-2. The output of each amplifier must stay 200mV away from the rails (AVDD and AVSS), otherwise the PGA becomes nonlinear. Consequently, the maximum output swing of the PGA is limited to VOUT = ±[(AVDD – AVSS) – 0.4V].

Using a 3mV/V load cell with a 5V excitation yields a maximum differential output voltage of VINMAX = ±15mV, which meets Equation 40 when using a gain of 128.

Equation 40. VINMAX ≤ ±[(AVDD – AVSS) – 0.4V] / Gain = ±(5V – 0.4V) / 128 = ±36mV

A first-order differential and common-mode RC filter (RF1, RF2, CDIF1, CCM1, and CCM2) is placed on the ADC inputs. The reference has an additional capacitor CDIF2 to limit reference noise. Care must be taken to maintain a limited amount of filtering or the measurement is no longer ratiometric.

To find the repeatability of the readings, perform the following calculation. The load cell produces an output voltage of 15mV at the maximum load of 1kg. At a Gain = 128 and DR = 20SPS the ADS1220 offers a noise-free resolution of 0.41µVpp. The repeatability is then calculated as shown in Equation 41.

Equation 41. Repeatability = (1kg / 15mV) × 0.41µV = 27mg

The register settings for this design are shown in Table 9-6.

Table 9-6 Register Settings
REGISTERSETTINGDESCRIPTION
00h3EhAINP = AIN1, AINN = AIN2, gain = 128, PGA enabled
01h04hDR = 20SPS, normal mode, continuous conversion mode
02h98hExternal reference (REFP1, REFN1), simultaneous 50Hz and 60Hz rejection, PSW = 1b
03h00hNo IDACs used