SBAS501D May   2013  – May 2026 ADS1220

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 Bypassing the PGA
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Clock Source
      5. 8.3.5  Modulator
      6. 8.3.6  Digital Filter
      7. 8.3.7  Output Data Rate
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Low-Side Power Switch
      10. 8.3.10 Sensor Detection
      11. 8.3.11 System Monitor
      12. 8.3.12 Offset Calibration
      13. 8.3.13 Temperature Sensor
        1. 8.3.13.1 Converting From Digital Codes to Temperature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Single-Shot Conversion Mode
        2. 8.4.2.2 Continuous Conversion Mode
      3. 8.4.3 Operating Modes
        1. 8.4.3.1 Normal Mode
        2. 8.4.3.2 Duty-Cycle Mode
        3. 8.4.3.3 Turbo Mode
        4. 8.4.3.4 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready ( DRDY)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Timeout
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 RESET (0000 011xb)
        2. 8.5.3.2 START/SYNC (0000 100xb)
        3. 8.5.3.3 POWERDOWN (0000 001xb)
        4. 8.5.3.4 RDATA (0001 xxxxb)
        5. 8.5.3.5 RREG (0010 rrnnb)
        6. 8.5.3.6 WREG (0100 rrnnb)
      4. 8.5.4 Reading Data
      5. 8.5.5 Sending Commands
      6. 8.5.6 Interfacing with Multiple Devices
    6. 8.6 Register Map
      1. 8.6.1 Configuration Registers
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1 Configuration Register 0 (Address = 00h) [reset = 00h]
        2. 8.6.2.2 Configuration Register 1 (Address = 01h) [reset = 00h]
        3. 8.6.2.3 Configuration Register 2 (Address = 02h) [reset = 00h]
        4. 8.6.2.4 Configuration Register 3 (Address = 03h) [reset = 00h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Unused Inputs and Outputs
      6. 9.1.6 Pseudo Code Example
    2. 9.2 Typical Applications
      1. 9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Resistive Bridge Measurement
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Ramp Rate
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.1 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is particularly useful when measuring low-level signals.

Table 7-1 to Table 7-8 summarize the device noise performance. Data are representative of typical noise performance at TA = 25°C using the internal 2.048V reference. Data shown are the result of averaging readings from a single device over a time period of approximately 0.75 seconds and are measured with the inputs internally shorted together. Table 7-1, Table 7-3, Table 7-5 and Table 7-7 list the input-referred noise in units of μVRMS for the conditions shown. Values in µVPP are shown in parenthesis. Table 7-2, Table 7-4, Table 7-6 and Table 7-8 list the corresponding data in effective resolution calculated from μVRMS values using Equation 1. Noise-free resolution calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.

The input-referred noise (Table 7-1, Table 7-3, Table 7-5 and Table 7-7) only changes marginally when using an external low-noise reference, such as the REF5020. Use Equation 1 and Equation 2 to calculate effective resolution numbers and noise-free resolution when using a reference voltage other than 2.048V:

Equation 1. Effective Resolution = ln [2 × VREF / (Gain × VRMS-Noise)] / ln(2)
Equation 2. Noise-Free Resolution = ln [2 × VREF / (Gain × VPP-Noise)] / ln(2)
Table 7-1 Noise in μVRMS (μVPP)
at AVDD = 3.3V, AVSS = 0V, Normal Mode, and Internal Reference = 2.048V
DATA RATE
(SPS)		 GAIN (PGA Enabled)
1 2 4 8 16 32 64 128
20 3.71 (13.67) 1.54 (5.37) 1.15 (4.15) 0.80 (3.36) 0.35 (1.16) 0.23 (0.73) 0.10 (0.35) 0.09 (0.41)
45 7.36 (29.54) 2.93 (13.06) 1.71 (9.28) 0.88 (4.06) 0.50 (2.26) 0.29 (1.49) 0.19 (0.82) 0.12 (0.51)
90 10.55 (47.36) 4.50 (20.75) 2.43 (11.35) 1.51 (6.65) 0.65 (3.62) 0.42 (2.14) 0.27 (1.22) 0.18 (0.85)
175 11.90 (63.72) 6.45 (34.06) 3.26 (17.76) 1.82 (11.20) 1.01 (5.13) 0.57 (3.09) 0.34 (2.14) 0.26 (1.60)
330 19.19 (106.93) 9.38 (50.78) 4.25 (26.25) 2.68 (14.13) 1.45 (7.52) 0.79 (4.66) 0.50 (2.69) 0.34 (1.99)
600 24.78 (151.61) 13.35 (72.27) 6.68 (39.43) 3.66 (19.26) 2.10 (12.77) 1.14 (6.87) 0.70 (4.76) 0.55 (3.34)
1000 37.53 (227.29) 18.87 (122.68) 9.53 (58.53) 5.37 (31.52) 2.95 (18.08) 1.65 (10.71) 1.03 (6.52) 0.70 (4.01)
Table 7-2 Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3V, AVSS = 0V, Normal Mode, and Internal Reference = 2.048V
DATA RATE
(SPS)		 GAIN (PGA Enabled)
1 2 4 8 16 32 64 128
20 20.08 (18.19) 20.34 (18.54) 19.76 (17.91) 19.28 (17.22) 19.48 (17.75) 19.10 (17.42) 19.33 (17.49) 18.49 (16.26)
45 19.09 (17.08) 19.42 (17.26) 19.19 (16.75) 19.15 (16.94) 18.95 (16.79) 18.74 (16.39) 18.38 (16.25) 18.00 (15.49)
90 18.57 (16.40) 18.80 (16.59) 18.68 (16.46) 18.37 (16.23) 18.60 (16.11) 18.20 (15.87) 17.87 (15.67) 17.44 (15.20)
175 18.39 (15.97) 18.28 (15.88) 18.26 (15.82) 18.10 (15.48) 17.96 (15.61) 17.78 (15.34) 17.53 (14.87) 16.91 (14.29)
330 17.70 (15.23) 17.74 (15.30) 17.88 (15.25) 17.54 (15.15) 17.43 (15.05) 17.30 (14.74) 16.96 (14.54) 16.50 (13.97)
600 17.33 (14.72) 17.23 (14.79) 17.23 (14.66) 17.09 (14.70) 16.89 (14.29) 16.77 (14.18) 16.48 (13.72) 15.83 (13.23)
1000 16.74 (14.14) 16.73 (14.03) 16.71 (14.09) 16.54 (13.99) 16.41 (13.79) 16.25 (13.54) 15.92 (13.26) 15.49 (12.96)
Table 7-3 Noise in μVRMS (μVPP) With PGA Disabled
at AVDD = 3.3V, AVSS = 0V, Normal Mode, and Internal Reference = 2.048V
DATA RATE
(SPS)		 GAIN (PGA Disabled)
1 2 4
20 3.89 (13.43) 1.85 (6.84) 1.26 (3.91)
45 6.97 (31.98) 2.94 (12.94) 1.41 (5.62)
90 8.50 (42.48) 4.49 (18.92) 2.07 (9.95)
175 12.99 (65.92) 6.24 (35.40) 3.04 (18.92)
330 18.18 (94.24) 8.12 (50.17) 4.71 (28.75)
600 25.29 (138.67) 12.77 (78.13) 6.27 (39.79)
1000 38.04 (260.50) 18.40 (120.97) 9.48 (63.72)
Table 7-4 Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise) With PGA Disabled at AVDD = 3.3V, AVSS = 0V, Normal Mode, and Internal Reference = 2.048V
DATA RATE
(SPS)		 GAIN (PGA Disabled)
1 2 4
20 20.01 (18.22) 20.08 (18.19) 19.63 (18.00)
45 19.61 (16.97) 19.41 (17.27) 19.47 (17.48)
90 18.88 (16.56) 18.80 (16.72) 18.91 (16.65)
175 18.27 (15.92) 18.32 (15.82) 18.36 (15.72)
330 17.78 (15.41) 17.94 (15.32) 17.73 (15.12)
600 17.31 (14.85) 17.29 (14.68) 17.32 (14.65)
1000 16.72 (13.94) 16.76 (14.05) 16.72 (13.97)
Table 7-5 Noise in μVRMS (μVPP)
at AVDD = 3.3V, AVSS = 0V, Turbo Mode, and Internal Reference = 2.048V
DATA RATE
(SPS)		 GAIN (PGA Enabled)
1 2 4 8 16 32 64 128
40 4.56 (24.17) 2.40 (11.35) 1.22 (4.94) 0.71 (2.84) 0.35 (1.60) 0.19 (0.85) 0.16 (0.71) 0.09 (0.55)
90 5.74 (25.88) 2.97 (14.40) 1.47 (5.80) 1.13 (5.52) 0.50 (2.67) 0.32 (1.32) 0.23 (1.13) 0.15 (0.69)
180 8.49 (46.88) 4.66 (21.36) 2.30 (12.88) 1.24 (7.23) 0.72 (4.82) 0.42 (2.57) 0.28 (1.47) 0.24 (1.34)
350 13.42 (84.72) 5.86 (40.04) 3.39 (19.04) 1.88 (10.13) 1.05 (6.15) 0.64 (3.59) 0.43 (2.29) 0.28 (1.39)
660 17.09 (120.36) 9.34 (47.36) 4.81 (27.83) 2.97 (17.36) 1.54 (10.21) 0.82 (4.43) 0.58 (3.67) 0.41 (2.93)
1200 25.71 (162.35) 12.31 (85.94) 6.81 (44.01) 3.72 (21.55) 2.09 (15.14) 1.23 (7.58) 0.80 (5.31) 0.57 (3.51)
2000 36.23 (265.14) 18.24 (127.32) 9.24 (65.43) 5.49 (37.02) 2.89 (18.89) 1.77 (12.00) 1.13 (7.60) 0.82 (5.81)
Table 7-6 Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3V, AVSS = 0V, Turbo Mode, and Internal Reference = 2.048V
DATA RATE
(SPS)		 GAIN (PGA Enabled)
1 2 4 8 16 32 64 128
40 19.78 (17.37) 19.71 (17.46) 19.68 (17.66) 19.45 (17.46) 19.47 (17.29) 19.37 (17.21) 18.65 (16.46) 18.40 (15.83)
90 19.45 (17.27) 19.39 (17.12) 19.41 (17.43) 18.79 (16.50) 18.97 (16.55) 18.62 (16.57) 18.11 (15.80) 17.75 (15.49)
180 18.88 (16.42) 18.75 (16.55) 18.76 (16.28) 18.65 (16.11) 18.43 (15.70) 18.23 (15.60) 17.79 (15.41) 17.05 (14.54)
350 18.22 (15.56) 18.42 (15.64) 18.21 (15.71) 18.05 (15.62) 17.89 (15.35) 17.62 (15.12) 17.20 (14.77) 16.78 (14.49)
660 17.87 (15.05) 17.74 (15.40) 17.70 (15.17) 17.39 (14.85) 17.34 (14.61) 17.25 (14.82) 16.75 (14.09) 16.25 (13.42)
1200 17.28 (14.62) 17.34 (14.54) 17.20 (14.51) 17.07 (14.54) 16.90 (14.05) 16.67 (14.04) 16.28 (13.56) 15.77 (13.15)
2000 16.79 (13.92) 16.78 (13.97) 16.76 (13.93) 16.51 (13.76) 16.44 (13.73) 16.14 (13.38) 15.79 (13.04) 15.25 (12.43)
Table 7-7 Noise in μVRMS (μVPP) With PGA Disabled
at AVDD = 3.3V, AVSS = 0V, Turbo Mode, and Internal Reference = 2.048V
DATA RATE
(SPS)		 GAIN (PGA Disabled)
1 2 4
40 4.22 (22.46) 2.30 (10.74) 0.93 (3.91)
90 6.57 (31.01) 3.53 (14.28) 1.59 (6.84)
180 8.41 (55.66) 4.30 (22.09) 2.31 (14.59)
350 12.68 (75.20) 6.02 (34.18) 3.22 (17.64)
660 17.81 (111.08) 9.06 (56.76) 4.24 (27.47)
1200 25.43 (176.03) 12.70 (89.23) 6.28 (40.95)
2000 36.11 (250.98) 17.30 (131.35) 8.77 (68.18)
Table 7-8 Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise) With PGA Disabled at AVDD = 3.3V, AVSS = 0V, Turbo Mode, and Internal Reference = 2.048V
DATA RATE
(SPS)		 GAIN (PGA Disabled)
1 2 4
40 19.89 (17.48) 19.76 (17.54) 20.07 (18.00)
90 19.25 (17.01) 19.15 (17.13) 19.29 (17.19)
180 18.89 (16.17) 18.86 (16.50) 18.76 (16.10)
350 18.30 (15.73) 18.38 (15.87) 18.28 (15.83)
660 17.81 (15.17) 17.79 (15.14) 17.88 (15.19)
1200 17.30 (14.51) 17.30 (14.49) 17.31 (14.61)
2000 16.79 (13.99) 16.85 (13.93) 16.83 (13.87)