SBASAL0A August   2025  â€“ October 2025 ADC34RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Monitor
      4. 7.3.4 ADC Power Down Modes
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly with Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly with Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.4 ADC Power Down Modes

The device supports three different power down modes that can be controlled via GPIO pins or SPI register writes:

  • Fast Power Down: individual channel power down with shorter wake up time but higher power consumption. JESD interface stays active.
  • Power Down: individual channel power down. JESD interface can be adjusted and power down unused lanes.
  • Global Power Down: power down of entire chip for lowest power consumption.
Table 7-6 Power Down Modes Comparison
Power Down Mode Wake Up Time Power Consumption (typ) Comment
Fast Power Down ~ 5 us ~ 2.2 W JESD interface stays active
Power Down depends on JESD interface ~ 0.8W (4ch powered down)
~ 2.6W (2ch powered down)
~ 3.8W (1ch powered down)		 JESD interface power down
4 Serdes lanes active
8 Serdes lanes active
Global Power Down depends on JESD interface ~ 0.4 W

The power down modes can be can be programmed using the following parameters:

Table 7-7 Power Down Modes Programming
System Parameter Name Size Default Access Description
ADC_SW_GPDN_VAL 1 0 R/W Select internal global power down state. ADC_GPDN_SRC_SEL needs to be set to 1 for this setting to take effect.

0: Device is powered up.

1: Device is powered down.
ADC_GPDN_SRC_SEL 1 0 R/W Select if global power down signal is coming from a GPIO or SPI.

0: Global power down is from GPIO.

1: Global power down is coming from ADC_SW_GPDN_VAL.
ADC_CH_PDN_VAL 4 0 R/W Individual ADC channel power down setting. Each ADC gets one bit. If the bit is set, the corresponding channel is powered down. ADC_CH_PDN_SRC_SEL needs to be set to 1 for this setting to take effect.

Bit 0: ADC0 power down control.

Bit 1: ADC1 power down control.

Bit 2: ADC2 power down control.

Bit 3: ADC3 power down control.
ADC_CH_PDN_SRC_SEL 1 0 R/W Select if channel power down signal is coming from a GPIO or SPI.

0: Channel power down is from GPIO.

1: Channel power down is coming from ADC_CH_PDN_VAL.
ADC_CH_PDN_MODE 1 0 R/W Select the channel power down mode.

0: Normal PDN (least power consumption for each channel).

1: Fast PDN (faster power up time but higher power consumption).