SBASAL0A August   2025  â€“ October 2025 ADC34RF72

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth
        2. 7.3.1.2 Background Calibration
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Monitor
      4. 7.3.4 ADC Power Down Modes
      5. 7.3.5 Digital Signal Processor (DSP) Features
        1. 7.3.5.1 DSP Input Mux
        2. 7.3.5.2 Fractional Delay
        3. 7.3.5.3 Programmable FIR Filter for Equalization
        4. 7.3.5.4 DSP Output Mux
        5. 7.3.5.5 Digital Down Converter (DDC)
          1. 7.3.5.5.1 Decimation Filter Input
          2. 7.3.5.5.2 Decimation Modes
          3. 7.3.5.5.3 Decimation Filter Response
          4. 7.3.5.5.4 Numerically Controlled Oscillator (NCO)
            1. 7.3.5.5.4.1 NCO Update
            2. 7.3.5.5.4.2 NCO RESET
      6. 7.3.6 Digital Output Interface
        1. 7.3.6.1 JESD204B/C Interface
          1. 7.3.6.1.1 JESD204B Initial Lane Alignment (ILA)
          2. 7.3.6.1.2 SYNC Signal
          3. 7.3.6.1.3 JESD204B/C Frame Assembly
          4. 7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode
          5. 7.3.6.1.5 JESD204B/C Frame Assembly with Real Decimation
          6. 7.3.6.1.6 JESD204B,C Frame Assembly with Complex Decimation
        2. 7.3.6.2 JESD Output Reference Clock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Operating Mode Comparison
    5. 7.5 Programming
      1. 7.5.1 GPIO Control
      2. 7.5.2 SPI Register Write
      3. 7.5.3 SPI Register Read
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application: Spectrum Analyzer
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Signal Path: Wideband Receiver
        2. 8.2.1.2 Clocking
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sampling Clock Requirements
      3. 8.2.3 Application Performance Plots
    3. 8.3 Typical Application: Time Domain Digitizer
      1. 8.3.1 Design Requirements
        1. 8.3.1.1 Input Signal Path: Time Domain Digitizer
      2. 8.3.2 Application Performance Plots
    4. 8.4 Initialization Set Up
    5. 8.5 Power Supply Recommendations
    6. 8.6 Layout
      1. 8.6.1 Layout Guidelines
      2. 8.6.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
      2. 9.1.2 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
7.3.6.1.4 JESD204B/C Frame Assembly in Bypass Mode

Table 7-19 lists the available JESD204B/C formats and corresponding valid sampling rate ranges for the ADC34RF7x. The sampling rates are limited by the minimum and maximum SERDES line rate as well as ADC sampling clock frequencies. The JESD204B/C frame assembly for the different lanes is shown in Table 7-20.

Table 7-19 JESD Mode Options: Bypass Mode
OUTPUT
RESOLUTION
(Bits)		 L M F S JESD204B:
Lane Rate (Gbps)		 JESD204B
RATIO
[fSERDES/FS]		 JESD204C:
Lane Rate (Gbps)		 JESD204C
RATIO
[fSERDES/FS]
16 8 4 1 1 FS x 16 x 10/8 x M / L 10 FS x 16 x 66 /64 x M / L 8.25
4 4 2 1 20 16.5
8 2 1 2 5 4.125
4 2 1 1 10 8.25
2 2 2 1 20 16.5
4 1 1 2 5 4.125
2 1 1 1 10 8.25
1 1 2 1 20 16.5
Table 7-20 Example JESD Sample Frame Assembly: Bypass Mode
OUTPUT
LANE		 LMFS = 8-4-1-1 LMFS = 4-4-2-1 LMFS = 8-2-1-2 LMFS = 4-2-1-1 LMFS = 2-2-2-1 LMFS = 4-1-1-2 LMFS = 2-1-1-1 LMFS = 1-1-2-1
STX0 A0[15:8] A0[15:0] A0[15:8] A0[15:8] A0[15:0] A0[15:8] A0[15:8] A0[15:0]
STX1 A0[7:0] B0[15:0] A0[7:0] A0[7:0] B0[15:0] A0[7:0] A0[7:0]
STX2 B0[15:8] C0[15:0] A1[15:8] B0[15:8] A1[15:8]
STX3 B0[7:0] D0[15:0] A1[7:0] B0[7:0] A1[7:0]
STX4 C0[15:8] B0[15:8]
STX5 C0[7:0] B0[7:0]
STX6 D0[15:8] B1[15:8]
STX7 D0[7:0] B1[7:0]