SBASAP4 April   2025 ADC3664-EP , ADC3664-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter Design
          2. 7.3.1.2.2 Analog Input Termination and DC Bias
            1. 7.3.1.2.2.1 AC-Coupling
            2. 7.3.1.2.2.2 DC-Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal voltage reference
        2. 7.3.3.2 External voltage reference (VREF)
        3. 7.3.3.3 External voltage reference with internal buffer (REFBUF/CTRL)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Output Formatter
        2. 7.3.5.2 Output Bit Mapper
          1. 7.3.5.2.1 2-Wire Mode
          2. 7.3.5.2.2 1-Wire Mode
          3. 7.3.5.2.3 ½-Wire Mode
        3. 7.3.5.3 Output Interface and Mode Configuration
          1. 7.3.5.3.1 Configuration Example
        4. 7.3.5.4 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal operation
      2. 7.4.2 Power Down Options
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.3.4.7 Output Formatting with Decimation

When using decimation, the output data is formatted as shown in Figure 7-32 and Figure 7-33. The examples are shown for 16-bit output for 2-wire (8x serialization), 1-wire (16x serialization) and 1/2-wire (32x serialization).

ADC3664-SEP ADC3664-EP Output Data Format in Complex DecimationFigure 7-32 Output Data Format in Complex Decimation

Table 7-3 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of SLVDS lanes (L) and complex decimation setting (N).

The table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output resolution and complex decimation by 4.

Table 7-3 Serial LVDS Lane Rate Examples with Complex Decimation and 16-bit Output Resolution
DECIMATION SETTINGADC SAMPLING RATEOUTPUT RESOLUTION# of WIRESFCLKDCLKIN, DCLKDA/B0,1
NFSRLFS / N[DA/B0,1] / 2FS x 2 x R / L / N
4125MSPS16231.25MHz250MHz500MHz
1500MHz1000MHz
55MSPS1/215.625MHz50MHz1000MHz
ADC3664-SEP ADC3664-EP Output Data Format in Real DecimationFigure 7-33 Output Data Format in Real Decimation

Table 7-4 illustrates the output interface data rate along with the corresponding DCLK/DCLKIN and FCLK frequencies based on output resolution (R), number of SLVDS lanes (L) and real decimation setting (M).

The table shows an actual lane rate example for the 2-, 1- and 1/2-wire interface, 16-bit output resolution and real decimation by 4.

Table 7-4 Serial LVDS Lane Rate Examples with Real Decimation and 16-bit Output Resolution
DECIMATION SETTINGADC SAMPLING RATEOUTPUT RESOLUTION# of WIRESFCLKDCLKIN, DCLKDA/B0,1
MFSRLFS / M / 2 (L = 2)
FS / M (L = 1, 1/2)		[DA/B0,1] / 2FS x R / L / M
4125MSPS16215.625MHz125 MHz250MHz
131.25MHz250MHz500MHz
1/2500MHz1000MHz