SBASAP4 April   2025 ADC3664-EP , ADC3664-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter Design
          2. 7.3.1.2.2 Analog Input Termination and DC Bias
            1. 7.3.1.2.2.1 AC-Coupling
            2. 7.3.1.2.2.2 DC-Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal voltage reference
        2. 7.3.3.2 External voltage reference (VREF)
        3. 7.3.3.3 External voltage reference with internal buffer (REFBUF/CTRL)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Output Formatter
        2. 7.3.5.2 Output Bit Mapper
          1. 7.3.5.2.1 2-Wire Mode
          2. 7.3.5.2.2 1-Wire Mode
          3. 7.3.5.2.3 ½-Wire Mode
        3. 7.3.5.3 Output Interface and Mode Configuration
          1. 7.3.5.3.1 Configuration Example
        4. 7.3.5.4 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal operation
      2. 7.4.2 Power Down Options
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Maps
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

8.2.1 Design Requirements

Frequency domain applications cover a wide range of frequencies from low input frequencies at or near DC in the 1st Nyquist zone to undersampling in higher Nyquist zones. If low input frequency is supported, the input has to be DC coupled and the ADC driven by a fully differential amplifier (FDA). If low frequency support is not needed, then AC coupling and use of a balun is more suitable.

The internal reference is used since DC precision is not needed. However, the ADC AC performance is highly dependent on the quality of the external clock source. If in-band interferes are present, then the ADC SFDR performance is a key care about as well. A higher ADC sampling rate is desirable to relax the external anti-aliasing filter. An internal decimation filter is used to reduce the digital output rate afterwards.

Table 8-1 Design key care-abouts
FEATUREDESCRIPTION
Signal BandwidthDC to 30MHz
Input DriverSingle ended to differential signal conversion and DC coupling
Clock SourceExternal clock with low jitter

When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into consideration. For example, the ADC3664-xEP input full-scale is 3.2Vpp. When factoring in approximately 1dB for insertion loss of the filter, then the amplifier needs to deliver close to 3.6Vpp. The amplifier distortion performance degrades with a larger output swing. Considering the ADC common mode input voltage, the amplifier may not be able to deliver the full swing. The ADC3664-xEP provides an output common mode voltage of 0.95V, and the THS4541 for example can only swing within 250mV of the negative supply. A unipolar 3.3V amplifier power supply limits the maximum voltage swing to approximately 2.8Vpp. If a larger output swing is required (factoring in filter insertion loss), then a negative supply for the amplifier is needed to eliminate that limitation. Additionally input voltage protection diodes is needed to protect the ADC from over-voltage events.

Table 8-2 Output voltage swing of THS4541 vs power supply
DEVICEMIN OUTPUT VOLTAGEMAX SWING WITH 3.3V/ 0V SUPPLYMAX SWING WITH 3.3V/ -1V SUPPLY
THS4541VS- + 250mV2.8Vpp6.8Vpp