SBASAY5A June   2024  – May 2025 ADS8681W , ADS8685W , ADS8689W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input Structure
      2. 6.3.2 Analog Input Impedance
      3. 6.3.3 Input Protection Circuit
      4. 6.3.4 Programmable Gain Amplifier (PGA)
      5. 6.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 6.3.6 ADC Driver
      7. 6.3.7 Reference
        1. 6.3.7.1 Internal Reference
        2. 6.3.7.2 External Reference
      8. 6.3.8 ADC Transfer Function
      9. 6.3.9 Alarm Features
        1. 6.3.9.1 Input Alarm
        2. 6.3.9.2 AVDD Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host-to-Device Connection Topologies
        1. 6.4.1.1 Single Device: All multiSPI Options
        2. 6.4.1.2 Single Device: Standard SPI Interface
        3. 6.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 6.4.2 Device Operational Modes
        1. 6.4.2.1 RESET State
        2. 6.4.2.2 ACQ State
        3. 6.4.2.3 CONV State
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Frame
      2. 6.5.2 Input Command Word and Register Write Operation
      3. 6.5.3 Output Data Word
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols With a Single SDO-x
          2. 6.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options
            2. 6.5.4.2.3.2 Output Bus Width Options
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 DEVICE_ID_REG Register (address = 00h)
      2. 7.1.2 RST_PWRCTL_REG Register (address = 04h)
      3. 7.1.3 SDI_CTL_REG Register (address = 08h)
      4. 7.1.4 SDO_CTL_REG Register (address = 0Ch)
      5. 7.1.5 DATAOUT_CTL_REG Register (address = 10h)
      6. 7.1.6 RANGE_SEL_REG Register (address = 14h)
      7. 7.1.7 ALARM_REG Register (address = 20h)
      8. 7.1.8 ALARM_H_TH_REG Register (address = 24h)
      9. 7.1.9 ALARM_L_TH_REG Register (address = 28h)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Alarm Function
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.1.7 ALARM_REG Register (address = 20h)

This register contains the output alarm flags (active and tripped) for the input and AVDD alarm.

The address for bits 7-0, 15-8, 23-16, and 31-24 is 20h, 21h, 22h, and 23h, respectively.

Figure 7-7 ALARM_REG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ACTIVE_VDD_L_FLAG ACTIVE_VDD_H_FLAG Reserved ACTIVE_IN_L_
FLAG		 ACTIVE_IN_H_
FLAG		 Reserved TRP_
VDD_L_
FLAG		 TRP_
VDD_H_
FLAG		 TRP_IN_L_FLAG TRP_IN_H_FLAG Reserved OVW_
ALARM
R-0b R-0b R-00b R-0b R-0b R-00b R-0b R-0b R-0b R-0b R-000b R-0b
Table 7-9 ALARM_REG Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0000h Reserved. Reads return 0000h.
15 ACTIVE_VDD_L_FLAG R 0b Active ALARM output flag for low AVDD voltage.
0b = No ALARM condition
1b = ALARM condition exists
14 ACTIVE_VDD_H_FLAG R 0b Active ALARM output flag for high AVDD voltage.
0b = No ALARM condition
1b = ALARM condition exists
13-12 Reserved R 00b Reserved. Reads return 00b.
11 ACTIVE_IN_L_FLAG R 0b Active ALARM output flag for low input voltage.
0b = No ALARM condition
1b = ALARM condition exists
10 ACTIVE_IN_H_FLAG R 0b Active ALARM output flag for high input voltage.
0b = No ALARM condition
1b = ALARM condition exists
9-8 Reserved R 00b Reserved. Reads return 00b.
7 TRP_VDD_L_FLAG R 0b Tripped ALARM output flag for low AVDD voltage.
0b = No ALARM condition
1b = ALARM condition exists
6 TRP_VDD_H_FLAG R 0b Tripped ALARM output flag for high AVDD voltage.
0b = No ALARM condition
1b = ALARM condition exists
5 TRP_IN_L_FLAG R 0b Tripped ALARM output flag for low input voltage.
0b = No ALARM condition
1b = ALARM condition exists
4 TRP_IN_H_FLAG R 0b Tripped ALARM output flag for high input voltage.
0b = No ALARM condition
1b = ALARM condition exists
3-1 Reserved R 000b Reserved. Reads return 000b.
0 OVW_ALARM R 0b Logical OR outputs all tripped ALARM flags.
0b = No ALARM condition
1b = ALARM condition exists