SBASAY5A June   2024  – May 2025 ADS8681W , ADS8685W , ADS8689W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input Structure
      2. 6.3.2 Analog Input Impedance
      3. 6.3.3 Input Protection Circuit
      4. 6.3.4 Programmable Gain Amplifier (PGA)
      5. 6.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 6.3.6 ADC Driver
      7. 6.3.7 Reference
        1. 6.3.7.1 Internal Reference
        2. 6.3.7.2 External Reference
      8. 6.3.8 ADC Transfer Function
      9. 6.3.9 Alarm Features
        1. 6.3.9.1 Input Alarm
        2. 6.3.9.2 AVDD Alarm
    4. 6.4 Device Functional Modes
      1. 6.4.1 Host-to-Device Connection Topologies
        1. 6.4.1.1 Single Device: All multiSPI Options
        2. 6.4.1.2 Single Device: Standard SPI Interface
        3. 6.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 6.4.2 Device Operational Modes
        1. 6.4.2.1 RESET State
        2. 6.4.2.2 ACQ State
        3. 6.4.2.3 CONV State
    5. 6.5 Programming
      1. 6.5.1 Data Transfer Frame
      2. 6.5.2 Input Command Word and Register Write Operation
      3. 6.5.3 Output Data Word
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols With a Single SDO-x
          2. 6.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options
            2. 6.5.4.2.3.2 Output Bus Width Options
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 DEVICE_ID_REG Register (address = 00h)
      2. 7.1.2 RST_PWRCTL_REG Register (address = 04h)
      3. 7.1.3 SDI_CTL_REG Register (address = 08h)
      4. 7.1.4 SDO_CTL_REG Register (address = 0Ch)
      5. 7.1.5 DATAOUT_CTL_REG Register (address = 10h)
      6. 7.1.6 RANGE_SEL_REG Register (address = 14h)
      7. 7.1.7 ALARM_REG Register (address = 20h)
      8. 7.1.8 ALARM_H_TH_REG Register (address = 24h)
      9. 7.1.9 ALARM_L_TH_REG Register (address = 28h)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Alarm Function
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5V, DVDD = 3.3V, VREF = 4.096V (internal), and maximum throughput (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
RIN Input impedance Input range = ±3 x VREF at TA = 25℃ 1.02 1.2 MΩ
Input range = ±2.5 x VREF at TA = 25℃ 0.85 1
Input range = ±1.5 x VREF at TA = 25℃ 1.02 1.2
Input range = ±1.25 x VREF at TA = 25℃ 0.85 1
Input range = ±0.625 x VREF at TA = 25℃ 0.85 1
Input range = 3 x VREF at TA = 25℃ 1.02 1.2
Input range = 2.5 x VREF at TA = 25℃ 0.85 1
Input range = 1.5 x VREF at TA = 25℃ 1.02 1.2
Input range = 1.25 x VREF at TA = 25℃ 0.85 1
IIN Input current Input range = ±3 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 2.5) / RIN µA
Input range = ±2.5 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 2.2) / RIN
Input range = ±1.5 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 2.0) / RIN
Input range = ±1.25 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 2.0) / RIN
Input range = ±0.625 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 1.6) / RIN
Input range = 3 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 2.6) / RIN
Input range = 2.5 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 2.5) / RIN
Input range = 1.5 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 2.7) / RIN
Input range = 1.25 x VREF with voltage at the AIN_P pin = VIN and AIN_M = GND (VIN – 2.5) / RIN
INPUT OVERVOLTAGE PROTECTION CIRCUIT
VOVP All input ranges AVDD = 5V, all input ranges –20 20 V
AVDD = Floating, all input ranges –15 15
INPUT BANDWIDTH
f–3 dB Small-signal Input bandwidth –3dB input range = ±3 x VREF 454 kHz
–3dB input range = ±2.5 x VREF 454
–3dB input range = ±1.5 x VREF 449
–3dB input range = ±1.25 x VREF 449
–3dB input range = ±0.625 x VREF 385
–3dB input range = 3 x VREF 414
–3dB input range = 2.5 x VREF 414
–3dB input range = 1.5 x VREF 368
–3dB input range = 1.25 x VREF 368
f–0.1 dB Small-signal Input bandwidth –0.1dB input range = ±3 x VREF 74 kHz
–0.1dB input range = ±2.5 x VREF 74
–0.1dB input range = ±1.5 x VREF 85
–0.1dB input range = ±1.25 x VREF 85
–0.1dB input range = ±0.625 x VREF 64
–0.1dB input range = 3 x VREF 75
–0.1dB input range = 2.5 x VREF 75
–0.1dB input range = 1.5 x VREF 83
–0.1dB input range = 1.25 x VREF 83
DC PERFORMANCE
Resolution 16 Bits
NMC No missing codes 16 Bits
DNL Differential nonlinearity All input ranges –0.9 ±0.6 0.9 LSB
INL Integral nonlinearity All input bipolar ranges –2 ±0.8 2 LSB
All unipolar ranges –2 ±0.6 2
EO Offset error All input bipolar ranges TA = 25°C –1.4 ±0.2 1.4 mV
All unipolar ranges TA = 25°C –2 ±0.2 2
Offset error drift with temperature All input ranges –3 ±0.75 3 ppm/℃
EG Gain error All input ranges at TA = 25°C –0.025 ±0.01 0.025 %FSR
Gain error drift with temperature All input ranges –5 ±1 5 ppm/℃
AC PERFORMANCE
SNR Signal-to-noise ratio Input range = ±3 x VREF 79 80.4 dB
Input range = ±2.5 x VREF 79 80.6
Input range = ±1.5 × VREF 78 79.3
Input range = ±1.25 × VREF 78 79.2
Input range = ±0.625 × VREF 76 77.2
Input range = 3 × VREF 77 78.8
Input range = 2.5 × VREF 77 78.8
Input range = 1.5 × VREF 76 77.5
Input range = 1.25 × VREF 76 77.3
THD Total harmonic distortion All input ranges  –105 dB
SINAD Signal-to-noise + distortion Input range = ±3 × VREF 79 80.4
dB
Input range = ±2.5 × VREF 79 80.6
Input range = ±1.5 × VREF 78 79.4
Input range = ±1.25 × VREF 78 79.3
Input range = ±0.625 × VREF 76 77.3
Input range = 3 × VREF 77 78.9
Input range = 2.5 × VREF 77 78.8
Input range = 1.5 × VREF 76 77.5
Input range = 1.25 × VREF 76 77.4
SFDR Spurious-free dynamic range All Input ranges 109
dB
INTERNAL REFERENCE OUTPUT
VREFIO On the REFIO pin (configured as an output) WQFN (RUM) at TA = 25℃ 4.094 4.096 4.098 V
dVREFIO/dTA Internal reference temperature drift 5 ppm/℃
COUT_REFIO Decoupling capacitor on REFIO pin 4.7 µF
VREFCAP Reference voltage to the ADC (on the REFCAP pin) 4.095 4.096 4.097 V
REFCAP temperature drift 0.5 2 ppm/℃
COUT_REFCAP Decoupling capacitor on REFCAP pin 10 µF
Turn-on time COUT_REFCAP = 10µF, COUT_REFIO = 10µF 20 ms
AVDD COMPARATOR
VTH_HIGH High threshold voltage 5.3 V
VTH_LOW Low threshold voltage 4.7
DIGITAL INPUTS (CMOS)
VIH Digital high input voltage logic level DVDD > 2.35V 0.7 × DVDD DVDD + 0.3 V
DVDD ≤ 2.35V 0.8 × DVDD DVDD + 0.3
VIL Digital lowinput voltage logic level DVDD > 2.35V –0.3 0.3 x DVDD V
DVDD ≤ 2.35V –0.3 0.2 x DVDD
Input leakage current 100 nA
Input pin capacitance 5 pF
DIGITAL OUTPUTS (CMOS)
VOH
Digital high output voltage logic level

 IO = 500μA source 0.8 × DVDD DVDD V
VOL
Digital low output voltage logic level

 IO = 500μA sink 0 0.2 × DVDD V

Floating state leakage current

 Only for digital output pins 1 µA

Internal pin capacitance

5 pF
POWER-SUPPLY REQUIREMENTS
AVDD Analog power-supply voltage Operating range 4.75 5 5.25 V
DVDD Digital power-supply voltage Operating range 1.65 3.3 AVDD V
Supply range for specified performance 2.7 3.3 AVDD
IAVDD_DYN Analog supply current, device converting at maximum throughput Internal reference ADS8681W 8.2 10.5 mA
Internal reference ADS8681W 5.6 7.25
Internal reference ADS8685W 4 5
External reference ADS8689W 7.0 8.75
External reference ADS8685W 4.4 5.5
External reference ADS8689W 2.7 3.25
IAVDD_STC Analog supply current, device not converting Internal reference ADS8681W 4.7 6.25 mA
Internal reference ADS8685W, ADS8689W 3.5 4.7
External reference ADS8681W 3.5 4.5
External reference ADS8685W, ADS8689W 2.3 3
IAVDD_STDBY Analog supply current, device in STANDBY mode Internal reference 2.8 mA
External reference 1.6
IAVDD_PD Analog supply current, device in PD mode Internal reference 10 µA
Enternal reference 10
IDVDD_DYN Digital supply current, maximum throughput 0.2 0.25 mA
IDVDD_STDBY Digital supply current, device in STANDBY mode 1 µA
IDVDD_PD Digital supply current, device in PD mode 1 µA