The device has an internal 4.096V (nominal value) reference. To select the internal reference, the REFSEL pin must be tied low or connected to AGND. When the internal reference is used, REFIO (pin 5) becomes an output pin with the internal reference value. Placing a 10µF (minimum) decoupling capacitor between the REFIO pin and REFGND (pin 6) is recommended, as shown in Figure 7-7. The capacitor must be placed as close to the REFIO pin as possible. The output impedance of the internal band-gap circuit creates a low-pass filter with this capacitor to band-limit the noise of the reference. The use of a smaller capacitor value allows higher reference noise in the system, thus degrading SNR and SINAD performance. Do not use the REFIO pin to drive external ac or dc loads because REFIO has limited current output capability. The REFIO pin can be used as a source if followed by a suitable op amp buffer (such as the OPA320).

Figure 7-7 Device Connections for Using an Internal 4.096V Reference

The device internal reference is trimmed to a maximum initial accuracy of ±1mV. The histogram in Figure 7-8 shows the distribution of the internal voltage reference output taken from more than 3300 production devices.

Figure 7-8 Internal Reference Accuracy at Room Temperature Histogram

The initial accuracy specification for the internal reference can be degraded if the die is exposed to any mechanical or thermal stress. Heating the device when being soldered to a PCB and any subsequent solder reflow is a primary cause for shifts in the V_REF value. The main cause of thermal hysteresis is a change in die stress and therefore is a function of the package, die-attach material, and molding compound, as well as the layout of the device.

To illustrate this effect, 80 devices are soldered using lead-free solder paste with the manufacturer's suggested reflow profile, as explained in the AN-2029 Handling and Process Recommendations application note. The internal voltage reference output is measured before and after the reflow process and the typical shift in value is shown in Figure 7-9. Although all tested units exhibit a positive shift in the output voltages, negative shifts are also possible. Note that the histogram in Figure 7-9 shows the typical shift for exposure to a single reflow profile. Exposure to multiple reflows, which is common on PCBs with surface-mount components on both sides, causes additional shifts in the output voltage. If the PCB is to be exposed to multiple reflows, solder the ADS868xW in the second pass to minimize device exposure to thermal stress.

Figure 7-9 Solder Heat Shift Distribution Histogram

The internal reference is also temperature compensated to provide excellent temperature drift over an extended industrial temperature range of –40°C to 125°C. Figure 7-10 shows the variation of the internal reference voltage across temperature for different values of the AVDD supply voltage. The typical specified value of the reference voltage drift over temperature is 8ppm/°C (Figure 7-11) and the maximum specified temperature drift is equal to 20ppm/°C.

Figure 7-10 Variation of the Internal Reference Output (REFIO) Across Supply and Temperature

AVDD = 5V, number of devices = 30, ΔT = –40°C to 125°C

Figure 7-11 Internal Reference Temperature Drift Histogram