SBASBC4A December   2025  – June 2026 ADS8688W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Overvoltage Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer (MUX)
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
      9. 7.3.9  Auxiliary Channel
        1. 7.3.9.1 Input Driver for the AUX Channel
      10. 7.3.10 ADC Transfer Function
      11. 7.3.11 Alarm Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface
        1. 7.4.1.1 Digital Pin Description
          1. 7.4.1.1.1 CS (Input)
          2. 7.4.1.1.2 SCLK (Input)
          3. 7.4.1.1.3 SDI (Input)
          4. 7.4.1.1.4 SDO (Output)
          5. 7.4.1.1.5 DAISY (Input)
          6. 7.4.1.1.6 RST / PD (Input)
        2. 7.4.1.2 Data Acquisition Example
        3. 7.4.1.3 Host-to-Device Connection Topologies
          1. 7.4.1.3.1 Daisy-Chain Topology
          2. 7.4.1.3.2 Star Topology
      2. 7.4.2 Device Modes
        1. 7.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 7.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 7.4.2.3 STANDBY Mode (STDBY)
        4. 7.4.2.4 Power-Down Mode (PWR_DN)
        5. 7.4.2.5 Auto Channel Enable With Reset (AUTO_RST)
        6. 7.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 7.4.2.7 Channel Sequencing Modes
        8. 7.4.2.8 Reset Program Registers (RST)
  9. 8 Register Maps
    1. 8.1 Command Register Description
    2. 8.2 Program Register Description
      1. 8.2.1 Program Register Read/Write Operation
      2. 8.2.2 Program Register Map
        1. 8.2.2.1 Auto-Scan Sequencing Control Registers
          1. 8.2.2.1.1 Auto-Scan Sequence Enable Register (address = 01h)
          2. 8.2.2.1.2 Channel Power Down Register (address = 02h)
        2. 8.2.2.2 Alarm Flag Registers (Read-Only)
          1. 8.2.2.2.1 ALARM Overview Tripped-Flag Register (address = 10h)
          2. 8.2.2.2.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
          3. 8.2.2.2.3 Alarm Threshold Setting Registers
        3. 8.2.2.3 Device Features Selection Control Register (address = 03h)
        4. 8.2.2.4 Range Select Registers (addresses 05h-0Ch)
        5. 8.2.2.5 Command Read-Back Register (address = 3Fh)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 78
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

5 Pin Configuration and Functions

Figure 5-1 DBT Package 38-Pin TSSOP Top View (Not to Scale)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
ADS8684W ADS8688W
1 SDI Digital input Data input for serial communication.
2 RST/ PD Digital input Active low logic input.
Dual functionality to reset or power-down the device.
3 DAISY Digital input Chain the data input during serial communication in daisy-chain mode.
4 REFSEL Digital input Active low logic input to enable the internal reference.
When low, the internal reference is enabled;
REFIO becomes an output that includes the VREF voltage.
When high, the internal reference is disabled;
REFIO becomes an input to apply the external VREF voltage.
5 REFIO Analog input, output Internal reference output and external reference input pin. Decouple with REFGND on pin 6.
6 REFGND Power supply Reference GND pin; short to the analog GND plane.
Decouple with REFIO on pin 5 and REFCAP on pin 7.
7 REFCAP Analog output ADC reference decoupling capacitor pin. Decouple with REFGND on pin 6.
8 AGND Power supply Analog ground pin. Decouple with AVDD on pin 9.
9 AVDD Power supply Analog supply pin. Decouple with AGND on pin 8.
10 AUX_INP Analog input Auxiliary input channel: positive input. Decouple with AUX_GND on pin 11.
11 AUX_GND Analog input Auxiliary input channel: negative input. Decouple with AUX_INP on pin 10.
12 NC AIN_6P Analog input Analog input channel 6, positive input. Decouple with AIN_6M on pin 13.
No connection for the ADS8684W; this pin can be left floating or connected to AGND.
13 NC AIN_6M Analog input Analog input channel 6, negative input. Decouple with AIN_6P on pin 12.
No connection for the ADS8684W; this pin can be left floating or connected to AGND.
14 NC AIN_7P Analog input Analog input channel 7, positive input. Decouple with AIN_7M on pin 15.
No connection for the ADS8684W; this pin can be left floating or connected to AGND.
15 NC AIN_7M Analog input Analog input channel 7, negative input. Decouple with AIN_7P on pin 14.
No connection for the ADS8684W; this pin can be left floating or connected to AGND.
16 AIN_0P Analog input Analog input channel 0, positive input. Decouple with AIN_0M on pin 17.
17 AIN_0M Analog input Analog input channel 0, negative input. Decouple with AIN_0P on pin 16.
18 AIN_1P Analog input Analog input channel 1, positive input. Decouple with AIN_1M on pin 19.
19 AIN_1M Analog input Analog input channel 1, negative input. Decouple with AIN_1P on pin 18.
20 AIN_2M Analog input Analog input channel 2, negative input. Decouple with AIN_2P on pin 21.
21 AIN_2P Analog input Analog input channel 2, positive input. Decouple with AIN_2M on pin 20.
22 AIN_3M Analog input Analog input channel 3, negative input. Decouple with AIN_3P on pin 23.
23 AIN_3P Analog input Analog input channel 3, positive input. Decouple with AIN_3M on pin 22.
24 NC AIN_4M Analog input Analog input channel 4, negative input. Decouple with AIN_4P on pin 25.
No connection for the ADS8684W; this pin can be left floating or connected to AGND.
25 NC AIN_4P Analog input Analog input channel 4, positive input. Decouple with AIN_4M on pin 24.
No connection for the ADS8684W; this pin can be left floating or connected to AGND.
26 NC AIN_5M Analog input Analog input channel 5, negative input. Decouple with AIN_5P on pin 27.
No connection for the ADS8684W; this pin can be left floating or connected to AGND.
27 NC AIN_5P Analog input Analog input channel 5, positive input. Decouple with AIN_5M on pin 26.
No connection for the ADS8684W; this pin can be left floating or connected to AGND.
28 AGND Power supply Analog ground pin
29 AGND Power supply Analog ground pin
30 AVDD Power supply Analog supply pin. Decouple with AGND on pin 31.
31 AGND Power supply Analog ground pin. Decouple with AVDD on pin 30.
32 AGND Power supply Analog ground pin.
33 DGND Power supply Digital ground pin. Decouple with DVDD on pin 34.
34 DVDD Power supply Digital supply pin. Decouple with DGND on pin 33.
35 ALARM Digital output Active high alarm output.
36 SDO Digital output Data output for serial communication.
37 SCLK Digital input Clock input for serial communication. Connect a 100Ω resistor in series close to the SCLK pin.
38 CS Digital input Active low logic input; chip-select signal.