SBASBC4A December   2025  – June 2026 ADS8688W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Overvoltage Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer (MUX)
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
      9. 7.3.9  Auxiliary Channel
        1. 7.3.9.1 Input Driver for the AUX Channel
      10. 7.3.10 ADC Transfer Function
      11. 7.3.11 Alarm Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface
        1. 7.4.1.1 Digital Pin Description
          1. 7.4.1.1.1 CS (Input)
          2. 7.4.1.1.2 SCLK (Input)
          3. 7.4.1.1.3 SDI (Input)
          4. 7.4.1.1.4 SDO (Output)
          5. 7.4.1.1.5 DAISY (Input)
          6. 7.4.1.1.6 RST / PD (Input)
        2. 7.4.1.2 Data Acquisition Example
        3. 7.4.1.3 Host-to-Device Connection Topologies
          1. 7.4.1.3.1 Daisy-Chain Topology
          2. 7.4.1.3.2 Star Topology
      2. 7.4.2 Device Modes
        1. 7.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 7.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 7.4.2.3 STANDBY Mode (STDBY)
        4. 7.4.2.4 Power-Down Mode (PWR_DN)
        5. 7.4.2.5 Auto Channel Enable With Reset (AUTO_RST)
        6. 7.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 7.4.2.7 Channel Sequencing Modes
        8. 7.4.2.8 Reset Program Registers (RST)
  9. 8 Register Maps
    1. 8.1 Command Register Description
    2. 8.2 Program Register Description
      1. 8.2.1 Program Register Read/Write Operation
      2. 8.2.2 Program Register Map
        1. 8.2.2.1 Auto-Scan Sequencing Control Registers
          1. 8.2.2.1.1 Auto-Scan Sequence Enable Register (address = 01h)
          2. 8.2.2.1.2 Channel Power Down Register (address = 02h)
        2. 8.2.2.2 Alarm Flag Registers (Read-Only)
          1. 8.2.2.2.1 ALARM Overview Tripped-Flag Register (address = 10h)
          2. 8.2.2.2.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
          3. 8.2.2.2.3 Alarm Threshold Setting Registers
        3. 8.2.2.3 Device Features Selection Control Register (address = 03h)
        4. 8.2.2.4 Range Select Registers (addresses 05h-0Ch)
        5. 8.2.2.5 Command Read-Back Register (address = 3Fh)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 78
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

7.3.3 Input Overvoltage Protection Circuit

The ADS868xW features an internal overvoltage protection circuit on each of the analog input channels. Use these protection circuits as a secondary protection scheme to protect the device. Using external protection devices against surges, electrostatic discharge (ESD), and electrical fast transient (EFT) conditions is highly recommended. The conceptual block diagram of the internal overvoltage protection (OVP) circuit is shown in Figure 7-2.

ADS8684W ADS8688W Input Overvoltage Protection Circuit Schematic Figure 7-2 Input Overvoltage Protection Circuit Schematic

As shown in Figure 7-2, the combination of the 1.2MΩ input resistors along with the PGA gain-setting resistors (RFB and RDC) limit the current flowing into the input pins. A combination of antiparallel diodes (D1 and D2) are added on each input pin to protect the internal circuitry and set the overvoltage protection limits.

Table 7-1 explains the various operating conditions for the device when the device is powered on. Table 7-1 indicates that when the AVDD pin of the device is connected to the proper supply voltage (AVDD = 5V) or offers a low impedance of < 30kΩ, the internal overvoltage protection circuit can withstand up to ±20V on the analog input pins.

Table 7-1 Input Overvoltage Protection Limits When AVDD = 5V or Offers a Low Impedance of < 30kΩ(1)
INPUT CONDITION
(VOVP = ±20V)		TEST CONDITIONADC OUTPUTCOMMENTS
|VIN| < |VRANGE|Within operating rangeAll input rangesValidDevice functions as per data sheet specifications
|VRANGE| < |VIN| < |VOVP|Beyond operating range but within overvoltage rangeAll input rangesSaturatedADC output is saturated, but device is internally protected (not recommended for extended time)
|VIN| > |VOVP|Beyond overvoltage rangeAll input rangesSaturatedThis usage condition can cause irreversible damage to the device
(1) GND = 0, AIN_nM = 0V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage for the internal OVP circuit. Assume that RS is approximately 0.

The results indicated in Table 7-1 are based on an assumption that the analog input pins are driven by very low impedance sources (RS is approximately 0). However, if the sources driving the inputs have higher impedance, the current flowing through the protection diodes reduces further, thereby increasing the OVP voltage range. Note that higher source impedance results in gain errors and contributes to overall system noise performance.

Figure 7-3 shows the voltage versus current response of the internal overvoltage protection circuit when the device is powered on. According to this current-to-voltage (I-V) response, the current flowing into the device input pins is limited by the 1.2MΩ input impedance. However, for voltages beyond ±20V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.

The same overvoltage protection circuit also provides protection to the device when the device is not powered on and AVDD is floating with an impedance > 30kΩ. This condition can arise when the input signals are applied before the ADC is fully powered on. The overvoltage protection limits for this condition are shown in Table 7-2.

Table 7-2 Input Overvoltage Protection Limits When AVDD = Floating with Impedance > 30kΩ(1)
INPUT CONDITION
(VOVP = ±11V)		TEST CONDITIONADC OUTPUTCOMMENTS
|VIN| < |VOVP|Within overvoltage rangeAll input rangesInvalidDevice is not functional but is protected internally by the OVP circuit.
|VIN| > |VOVP|Beyond overvoltage rangeAll input rangesInvalidThis usage condition can cause irreversible damage to the device.
(1) AVDD = floating, GND = 0, AIN_nM = 0V, |VRANGE| is the maximum input voltage for any selected input range, and |VOVP| is the break-down voltage for the internal OVP circuit. Assume that RS is approximately 0.

Figure 7-4 shows the voltage versus current response of the internal overvoltage protection circuit when the device is not powered on. According to this I-V response, the current flowing into the device input pins is limited by the 1.2MΩ input impedance. However, for voltages beyond ±11V, the internal node voltages surpass the break-down voltage for internal transistors, thus setting the limit for overvoltage protection on the input pins.

ADS8684W ADS8688W I-V Curve for an Input OVP Circuit (AVDD = 5V)Figure 7-3 I-V Curve for an Input OVP Circuit (AVDD = 5V)
ADS8684W ADS8688W I-V Curve for an Input OVP Circuit (AVDD = Floating)Figure 7-4 I-V Curve for an Input OVP Circuit (AVDD = Floating)