SBASBC4A December   2025  – June 2026 ADS8688W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Overvoltage Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer (MUX)
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
      9. 7.3.9  Auxiliary Channel
        1. 7.3.9.1 Input Driver for the AUX Channel
      10. 7.3.10 ADC Transfer Function
      11. 7.3.11 Alarm Feature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface
        1. 7.4.1.1 Digital Pin Description
          1. 7.4.1.1.1 CS (Input)
          2. 7.4.1.1.2 SCLK (Input)
          3. 7.4.1.1.3 SDI (Input)
          4. 7.4.1.1.4 SDO (Output)
          5. 7.4.1.1.5 DAISY (Input)
          6. 7.4.1.1.6 RST / PD (Input)
        2. 7.4.1.2 Data Acquisition Example
        3. 7.4.1.3 Host-to-Device Connection Topologies
          1. 7.4.1.3.1 Daisy-Chain Topology
          2. 7.4.1.3.2 Star Topology
      2. 7.4.2 Device Modes
        1. 7.4.2.1 Continued Operation in the Selected Mode (NO_OP)
        2. 7.4.2.2 Frame Abort Condition (FRAME_ABORT)
        3. 7.4.2.3 STANDBY Mode (STDBY)
        4. 7.4.2.4 Power-Down Mode (PWR_DN)
        5. 7.4.2.5 Auto Channel Enable With Reset (AUTO_RST)
        6. 7.4.2.6 Manual Channel n Select (MAN_Ch_n)
        7. 7.4.2.7 Channel Sequencing Modes
        8. 7.4.2.8 Reset Program Registers (RST)
  9. 8 Register Maps
    1. 8.1 Command Register Description
    2. 8.2 Program Register Description
      1. 8.2.1 Program Register Read/Write Operation
      2. 8.2.2 Program Register Map
        1. 8.2.2.1 Auto-Scan Sequencing Control Registers
          1. 8.2.2.1.1 Auto-Scan Sequence Enable Register (address = 01h)
          2. 8.2.2.1.2 Channel Power Down Register (address = 02h)
        2. 8.2.2.2 Alarm Flag Registers (Read-Only)
          1. 8.2.2.2.1 ALARM Overview Tripped-Flag Register (address = 10h)
          2. 8.2.2.2.2 Alarm Flag Registers: Tripped and Active (address = 11h to 14h)
          3. 8.2.2.2.3 Alarm Threshold Setting Registers
        3. 8.2.2.3 Device Features Selection Control Register (address = 03h)
        4. 8.2.2.4 Range Select Registers (addresses 05h-0Ch)
        5. 8.2.2.5 Command Read-Back Register (address = 3Fh)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Phase-Compensated, 8-Channel, Multiplexed Data Acquisition System for Power Automation
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 78
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

6.5 Electrical Characteristics

all minimum and maximum specifications are at TA = –40°C to +125°C; typical specifications are at TA = 25°C; AVDD = 5V, DVDD = 3.3V, VREF = 4.096V (internal), and maximum throughput (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
RIN Input impedance All input ranges at AIN_nP pin = VIN and AIN_nM = GND 1.02 1.2 MΩ
IIN Input current Input range = ±3 × VREF with voltage at the AIN_nP pin = VIN and AIN_nM = GND (VIN – 2.5) / RIN µA
Input range = ±1.5 × VREF with voltage at the AIN_nP pin = VIN and AIN_nM = GND (VIN – 2.0) / RIN
Input range = ±0.75 × VREF with voltage at the AIN_nP pin = VIN and AIN_nM = GND (VIN – 1.6) / RIN
Input range = 3 × VREF with voltage at the AIN_nP pin = VIN and AIN_nM = GND (VIN – 2.6) / RIN
Input range = 1.5 × VREF with voltage at the AIN_nP pin = VIN and AIN_nM = GND (VIN – 2.7) / RIN
INPUT OVERVOLTAGE PROTECTION CIRCUIT
VOVP All input ranges AVDD = 5V, all input ranges –20 20 V
AVDD = Floating, all input ranges –15 15
INPUT BANDWIDTH
f–3 dB Small-signal Input bandwidth, –3dB All input ranges at TA = 25°C 15 kHz
f–0.1 dB Small-signal Input bandwidth, –0.1dB All input ranges at TA = 25°C 2.5 kHz
DC PERFORMANCE
Resolution 16 Bits
NMC No missing codes 16 Bits
DNL Differential nonlinearity All input ranges –0.9 ±0.6 0.9 LSB
INL Integral nonlinearity All input bipolar ranges –2 ±0.8 2 LSB
All unipolar ranges –2 ±0.6 2
EO Offset error Bipolar ranges = ±3 × VREF and ±1.5 × VREF, TA = 25°C –1.8 ±0.2 1.8 mV
EO Bipolar range = ±0.75 × VREF, TA = 25°C –4.5 ±0.2 4.5 mV
Unipolar ranges = 3 × VREF and 1.5 × VREF, TA = 25°C –2.4 ±0.2 2.4
Offset error drift with temperature All input ranges –4.5 ±0.75 4.5 ppm/℃
EG Gain error All input ranges at TA = 25°C –0.05 ±0.01 0.05 %FSR
Gain error drift with temperature All input ranges –5 ±1 5 ppm/℃
AC PERFORMANCE
SNR Signal-to-noise ratio Input range = ±3 × VREF 89.5 91.5 dB
Input range = ±1.5 × VREF 88.5 90.5
Input range = ±0.75 × VREF 85.5 87.8
Input range = 3 × VREF 87.9 90
Input range = 1.5 × VREF 85.5 87.8
THD Total harmonic distortion All input ranges  –102 dB
SINAD Signal-to-noise + distortion Input range = ±3 × VREF 87.2 91
dB
Input range = ±1.5 × VREF 86.8 90
Input range = ±0.75 × VREF 83.5 86.5
Input range = 3 × VREF 85.7 89.5
Input range = 1.5 × VREF 83.3 86.4
SFDR Spurious-free dynamic range All Input ranges 103
dB
Crosstalk isolation(1) Aggressor channel input is overdriven to 2 × maximum input voltage 110 dB
Crosstalk memory(2) Aggressor channel input is overdriven to 2 × maximum input voltage 90 dB
AUXILIARY CHANNEL
Resolution 16 Bits
VAUX_IN AUX_IN voltage range (AUX_INP – AUX_GND) 0 VREF V
Operating input range AUX_INP 0 VREF V
AUX_GND 0
Input capacitance During sampling 75 pF
During conversion 5
Input leakage current 100 nA
Differential nonlinearity –0.99 1.5 LSB
Integral nonlinearity –4 4 LSB
Gain error at TA = 25°C ±0.2 %FSR
Offset error at TA = 25°C –10 10 mV
Signal-to-noise ratio VAUX_IN = -0.5dBFS at 1kHz 87 89 dB
Total harmonic distortion VAUX_IN = -0.5dBFS at 1kHz –102 dB
Signal-to-noise + distortion VAUX_IN = -0.5dBFS at 1kHz 86 88.5 dB
Spurious-free dynamic range VAUX_IN = -0.5dBFS at 1kHz 103 dB
INTERNAL REFERENCE OUTPUT
VREFIO On the REFIO pin (configured as an output) TA = 25℃ 4.092 4.096 4.1 V
dVREFIO/dTA Internal reference temperature drift 5 ppm/℃
COUT_REFIO Decoupling capacitor on REFIO pin 4.7 µF
VREFCAP Reference voltage to the ADC (on the REFCAP pin) 4.092 4.096 4.1 V
Reference buffer output impedance 0.5 1 Ω
Reference buffer temperature drift 0.5 1.5 ppm/℃
COUT_REFCAP Decoupling capacitor on REFCAP pin 10 22 µF
Turn-on time COUT_REFCAP = 10µF, COUT_REFIO = 10µF 20 ms
DIGITAL INPUTS
VIH Digital high input voltage logic level DVDD > 2.1V 0.7 × DVDD DVDD + 0.3 V
DVDD ≤ 2.1V 0.8 × DVDD DVDD + 0.3
VIL Digital low input voltage logic level DVDD > 2.1V –0.3 0.3 x DVDD V
DVDD ≤ 2.1V –0.3 0.2 x DVDD
Input leakage current 100 nA
Input pin capacitance 5 pF
DIGITAL OUTPUTS
VOH
Digital high output voltage logic level

 IO = 500μA source 0.8 × DVDD DVDD V
VOL
Digital low output voltage logic level

 IO = 500μA sink 0 0.2 × DVDD V

Floating state leakage current

 Only for SDO 1 µA

Internal pin capacitance

5 pF
POWER-SUPPLY REQUIREMENTS
IAVDD_DYN Analog supply current, device converting at maximum throughput with internal reference ADS8688W 13 16 mA
ADS8684W 8.5 11.5
IAVDD_STC Analog supply current, device not converting with internal reference ADS8688W 10 12 mA
ADS8684W 5.5 8.5
IAVDD_STDBY Analog supply current, device in STANDBY mode Device in STDBY mode and internal reference 3 4.5 mA
IAVDD_PD Analog supply current, device in PD mode Device in PWR_DN mode 3 20 µA
IDVDD_DYN Digital supply current, maximum throughput at DVDD = 3.3V, output = 0000h 0.5 mA
(1) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10kHz to a channel, not selected in the multiplexing sequence, and measuring the effect on the output of any selected channel.
(2) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10kHz to a channel, which is selected in the multiplexing sequence, and measuring the effect on the output of the next selected channel, for all combinations of input channels.