SBAU491 May   2025 ADS9326 , ADS9327

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 ADS9327EVM Quick Start Guide
    2. 2.2 Analog Interface
      1. 2.2.1 Fully-Differential Circuit: THS4552
      2. 2.2.2 Voltage Reference
    3. 2.3 Power Supplies
      1. 2.3.1 USB Power and When to Power the Board Externally
  9. 3Software
    1. 3.1 Digital Interface and Clock Inputs
      1. 3.1.1 Digital Interface Connections
      2. 3.1.2 Clock Select
    2. 3.2 ADS9327EVM Software Reference
      1. 3.2.1 ADS9327EVM-GUI Software Installation
      2. 3.2.2 Using the CONFIG Tab
      3. 3.2.3 Using the Capture Tab
      4. 3.2.4 Using the INL/DNL Tool
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials (BOM)
  11. 5Additional Information
    1. 5.1 Trademarks
  12. 6Related Documentation

3.1.2 Clock Select

The ADS9327EVM provides two options for supplying the conversion clock to the ADS9327: either a clock signal from the TSWDC155EVM or an external clock source. Table 3-1 and Figure 3-2 provide an overview of the ADS9327 sample clock options available on the EVM. By default, the FPGA controller on the TSWDC155EVM (sold separately) sources a clock that connects directly to the SMPL_CLKP pin on the ADS9327 by configuring J3 in the [2-3] position. The default configuration allows users to select the clock frequency from the options listed in the EVM GUI.

When using an external clock, move J3 into the [1-2] position and connect the external clock source to the SMA connector, J1. To maximize the performance of the ADS9327, establish that any external clock source has low jitter.

Table 3-1 Sample Clock Settings for ADS9327EVM
Sample Clock Source (SMPL_CLK) J1

J3

(SMPL_CLKP)

 R1
TSWDC155EVM — [2-3] Not installed
External Installed [1-2] Not installed

ADS9327EVM Sample Clock Selection Figure 3-2 Sample Clock Selection