SBOA362A December 2019 – October 2026 REF34 , REF34-Q1 , REF3425-EP , REF3430-EP , REF3433-EP , REF3440-EP , REF4132-Q1 , REF50 , REF5020-EP , REF5020A-Q1 , REF5025-EP , REF5025-HT , REF5025A-Q1 , REF5030A-Q1 , REF5040-EP , REF5040A-Q1 , REF5045A-Q1 , REF5050-EP , REF5050A-Q1 , REF50E , REF70
Load regulation is the measure of the variation in VREF as a function of load current. It is specified either as a percentage, or in parts-per-million per milliamp (ppm/mA). It is calculated by dividing the relative change in VREF at the minimum and maximum load currents by the range of the load current. Load regulation depends on both the reference design and the parasitic resistance separating it from the load, so the reference must be placed as close to the load as the PCB layout allows.
The impedance of the reference input is large enough (> 10 kΩ) on many data converters that load regulation error may not be significant. Maximum load current information can be found in ADC or DAC data sheets as either a minimum reference pin resistance (RREF), or a maximum reference current (IREF). In situations where the reference is buffered with a high-speed op amp, load regulation error can usually be ignored. Line regulation applies only to series voltage references, and is the measure of the change in the reference voltage as a function of the input voltage. The importance of line regulation depends on the tolerance of the input supply, and may not contribute significantly to the total error in when the input voltage tolerance is within 10% or less.
As with line regulation, PSRR importance depends on input supply specifics. For example, the PSRR can be critical if the VIN is noisy due to a switching regulator, is sensitive to EMI, and is subject to large load transients.