SBOA362A December   2019  – October 2026 REF34 , REF34-Q1 , REF3425-EP , REF3430-EP , REF3433-EP , REF3440-EP , REF4132-Q1 , REF50 , REF5020-EP , REF5020A-Q1 , REF5025-EP , REF5025-HT , REF5025A-Q1 , REF5030A-Q1 , REF5040-EP , REF5040A-Q1 , REF5045A-Q1 , REF5050-EP , REF5050A-Q1 , REF50E , REF70

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Voltage Reference Architecture
    1. 2.1 Shunt or Series Reference
    2. 2.2 Choosing the Best System Reference
  6. 3Key Specifications for Voltage Reference
    1. 3.1 Temperature Coefficient
    2. 3.2 Initial Accuracy
    3. 3.3 0.1–10 Hz Peak-to-peak Noise
    4. 3.4 Thermal Hysteresis and Long-term Stability
    5. 3.5 Load and Line Regulation
  7. 4Method of Negative Output Design and Noise Analysis
    1. 4.1 Voltage Inverting by Level Shift using REF5025 and OPA192
    2. 4.2 Using a Buffer to Generate Negative Reference Output
    3. 4.3 A Way to Minimize the Noise
  8. 5Conclusion
  9. 6References
  10. 7Revision History

4.1 Voltage Inverting by Level Shift using REF5025 and OPA192

For the DAC8801 reference input to generate positive DAC output, about -2.5-V negative output reference and negative output circuit configuration must be created first. Figure 4-2 shows a circuit that inverts output voltage from positive to negative. The output is feedback to the op amp input. The ground level on the REF5025 is tied to the op amp output, which shifts the positive level to negative. This is implemented by using an inverting circuit for a negative reference output. According to the noise level simulation graph in Figure 4-2, the output is -2.5 V. With this circuit, VREF negative output noise is about 210 nV/rtHz at 10 KHz.

REF34 Level Shifting Circuit and Noise Analysis ResultFigure 4-2 Level Shifting Circuit and Noise Analysis Result