SBOA602 November   2024 OPA593

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Current Booster, Push-Pull Topology Output Characteristics
    1. 2.1 Open-Loop Output Impedance
    2. 2.2 Minimizing Zero Crossover Distortion
  6. 3Various Current Booster Configurations
    1. 3.1 Complementary MOSFET versus BJT Current Booster Comparisons
  7. 4Stabilizing a Design for Power Amplifier Driving 1μF Capacitive Load (CL)
    1. 4.1 Op-Amp Driving Resistive Load
    2. 4.2 Op-Amp Driving Capacitive Load and Challenges
    3. 4.3 Open-Loop AC Stability Analysis - Compensating CL Effects Using DFC
    4. 4.4 Closed-Loop Stability Response - Small Signal Step Transient Analysis
    5. 4.5 Effects of Riso on Frequency Response in Dual Feedback Compensation
    6. 4.6 Summary of the DFC Technique
  8. 5Stabilizing the OPA593 and Darlington Current Booster for 1μF Capacitive Load
    1. 5.1 Open-Loop AC Stability Analysis - Composite Op-Amp Driving 1μF CL
    2. 5.2 Closed-Loop Stability Response - Composite Op-Amp's Step Transient Analysis
  9. 6Composite Amplifier's Effective BW and Step Time Response
  10. 7Test Bench Validation
  11. 8Summary
  12. 9References

4.1 Op-Amp Driving Resistive Load

In the simulator, an ideal power amplifier is modified to demonstrate the DFC compensation technique. Table 4-1 summarizes the key parameters of this modified power amplifier (PA). The simulation results in Figure 4-1 validate the model's behavior and confirm its consistency with the SPICE model. The unity gain bandwidth calculated from the gain bandwidth product (GBP) is approximately 1.2MHz, while the phase margin is approximately 88.6°.

Table 4-2 Emulated PA Design Requirements for Driving 1µF Capacitive Load
Design ParametersDesign Specification
ATE design requirementsHigh accuracy, programmable voltage regulators
Input voltage rangeInput swing up to ±5Vdc
Output voltage rangeOutput swing up to ±40Vdc
Output current rangeDriving current up to ±1Adc
Output resistive loadRL ≥ 40Ω
Closed-loop gains8V/V
Output impedanceLow open-loop output impedance, Zo = 1Ω across all frequencies
Output capacitive loadLow ESR (20mΩ), 1µF ceramic capacitive load and DUT
Effective bandwidthApproximately 50kHz, cutoff frequency at the –3dB point
Step time behaviorOutput rising-and-falling edge step-time response <100µs
Power regulationOutput voltage accuracy: approximately 0.05% or better at full scale