The DFC technique for compensating capacitive loads is complex. One challenge in optimizing DFC is that the effective bandwidth often exhibits gain peaking or Q effects in the AC frequency response. Gain peaking or a high Q factor indicates that more than one pole is present within the UGBW, a phenomenon characteristic of the DFC method, as illustrated in Figure 4-8. Gain peaking occurs when poles are closely spaced or overlapped within the closed feedback loop, resulting in resonant responses that elevate gains. This effect is observable only when the feedback loop is closed, whether in the time or frequency domain.

In the op-amp compensated for 1µF capacitive load, as depicted in Figure 4-8, the resistance R_iso values are progressively increased from 100mΩ, 500mΩ, 1Ω, and 5Ω. The selection of R_iso​ is relative to the op-amp’s open-loop output impedance, defined at 1Ω across all frequencies in the emulated Spice model. As R_iso increases, the additional pole f_p2 shifts toward lower frequencies, as described by Equation 4. This pole shift contributes to gain peaking in the frequency response when the newly emerged pole moves closer to the dominant pole, f_{DFC_BW}​ defined in the DFC loop. Gain peaking occurs when these two poles overlap or come too close together, as shown in Figure 4-8.

To optimize the value of R_iso in the DFC technique and eliminate guesswork, Equation 3 is used to calculate R_iso, based on the following Determine Optimal Isolation Resistance for Driving Capacitive Load, application note. The R_iso value must be significantly lower than both Zo and R_F​ parameters. A larger R_iso value can adversely affect the gain peaking or quality factor (Q) of the compensation loop, potentially altering the circuit's stability and effective bandwidth.

Figure 4-8 Effect of R_iso of the Compensated Op-Amp Driving 1μF Capacitive Load