How to adequately compensate capacitive loads in op-amps is well documented in the Precision Lab Series: Op Amps. This video series provides an overview of theories, simulations, examples and application notes.

One technique covered is the Dual Feedback Compensation (DFC) method, commonly used to compensate for complex loads in op-amps. However, detailed information on this technique is limited, particularly concerning current booster configurations like the OPA593 combined with a current booster driver.

The DFC technique mitigates the effects of capacitive loads, as demonstrated in Figure 4-2. This method involves placing an isolation resistor in series with the op-amp’s output or within the feedback path. The combination of the op-amp’s output impedance (Z_o + R_iso​) with the capacitive load (​C_L) introduces an additional pole (f_p2​), derived from Equation 4.

To estimate R_iso​, use the provided equation and select the nearest standard resistor value. In this example, the gain bandwidth product is defined at 10MHz, with a gain of 8V/V. The op-amp's closed-loop dominant pole (f_dom, 10MHz/8) is calculated to be 1.25MHz. The emulated op-amp’s open-loop output impedance, Z_o, is modeled at 1Ω across all frequencies, and R_iso is determined to be 356.8mΩ, approximately 357mΩ, as calculated from Equation 3.

The open-loop AC loop analysis focuses on determining the UGBW, loop gain, phase margins and other small signal stability parameters, as shown in Figure 4-2. Next, the compensated op-amp configuration is simulated to verify the circuit's closed-loop stability. This verification is achieved by applying a small step transient signal at the op-amp input during closed-loop operation. Making sure of the stability of an op-amp driving a complex load requires at least two simulation steps. The loop-stability iteration process optimizes the compensation between open-loop AC characteristics and closed-loop feedback responses. Without the proper step sequence, the op-amp's closed-loop behavior is undetermined, and output oscillatory behavior can manifest, as the uncompensated op-amp demonstrated in Figure 4-3.

Figure 4-2 Open-Loop AC Analysis of an Uncompensated Op-amp With R_iso

When an op-amp feedback system drives a capacitive load, understanding the interaction between the open-loop output impedance and the load capacitance is crucial. The emulated power amplifier’s open-loop output impedance, Z_o, is defined at 1Ω across all frequencies.

When driving 1μF capacitive load, a newly generated pole is calculated to be approximately 118kHz, as presented in Equation 4. Without the capacitive load, the unity gain bandwidth, f_unity, was simulated at 1.25MHz with a phase margin of 88.6°, as shown in Figure 4-1. Introducing the capacitive load causes f_unity to decrease, reducing the op-amp's roll-off slope from -20dB/decade to -40dB/decade, and the UGBW from 1.25MHz to approximately 374kHz. This additional pole reduces the phase margin from 88.6° to 17.4°, limiting the overall bandwidth of the system.

Figure 4-3 Uncompensated Op-Amp Driving 1μF Load - Unstable

To stabilize the feedback loop in Figure 4-2, set the additional f_p2 pole frequency approximately 1 to 2 octaves lower than the simulated 374kHz. With the effective bandwidth defined at 50kHz in Table 4-2, we assign this value to f_{DFC_BW} and calculate C_F using Equation 5, estimating the result to be approximately 455pF. A standard capacitor value of 420pF is selected, as shown in Figure 4-4.

Figure 4-4 Outer Feedback Loop Compensation Bode Plot Driving (Z_o + R_iso )∥R_L and C_L

The effective bandwidth of the DFC technique refers to the frequency range in which the op-amp achieves the desired gains and performance. In a dual feedback compensation topology, the op-amp bandwidth is not determined by the gain bandwidth product (GBP); instead, the effective bandwidth is primarily influenced by external compensation components, such as R_iso, R_F and C_F, as illustrated in Figure 4-5 and described in Equation 5. The compensation of the outer pole in the feedback loop, represented as approximately 1/sR_FC_F, defines the effective bandwidth (f_{DFC_BW}) of the DFC configuration.

Figure 4-5 DFC Overall Open-Loop AC Analysis: 2.6MHz UGBW and Phase Margin 89°