When a capacitive load of C_L = 1μF is introduced at the output of the current booster stage, a second pole, f_p2, is estimated to occur at approximately 320kHz, as determined by Equation 4. This pole falls within the UGBW, measured at 549kHz, resulting in significant phase lag and reducing the phase margin from 79° to –19.4°, as illustrated in Figure 5-2. Consequently, the combination of the OPA593 and the current booster becomes unstable when driving 1μF capacitive load in the closed-loop configuration.

Figure 5-2 OPA593 + Current Booster's Outer Feedback Loop AC Analysis - Driving 1μF (C_L)∥100Ω (R_L)

To stabilize the outer feedback loop, it is crucial to account for the additional pole, f_p2, at approximately 320kHz, arising from the interaction between Z_CBO (~0.5Ω) and C_L. A common technique in DFC is to reduce the outer loop-gain by incorporating a compensation capacitor, C_F. This capacitor ensures that the outer loop's UGBW is at least 1-2 octaves below f_p2. A conservative guideline recommends setting the outer loop's UGBW two octaves below f_p2, translating to less than 100kHz, to maintain stability within the multiple feedback loop compensation scheme. While larger values of C_F can improve overall DFC stability, they also significantly limit the circuit’s effective bandwidth, creating a trade-off that designers must carefully evaluate based on application requirements. Other DFC methods, primarily involving pole-zero cancellation, can also effectively address the pole that appears at the outer feedback loop's UGBW. However, detailed compensation procedures are beyond the scope of this application note.

According to the design requirements outlined in Table 2-2 and Equation 5, the target cutoff frequency, f_{DFC_CB_BW}, is defined at approximately 50kHz. To achieve this specification, the compensation capacitor, C_F is calculated to be around 455pF. The closest standard value, C_F ≈ 420pF, is then chosen. As shown in Figure 5-3, the simulated outer feedback loop’s UGBW is measured at 50.8kHz, with a phase margin of approximately 76°, based on the open-loop AC analysis. Consequently, the outer feedback loop is expected to remain stable during closed-loop operation, as indicated by the perturbation injection analysis.

Figure 5-3 OPA593 + Current Booster Composite Amplifier's Outer Feedback Loop Stability

As mentioned in the Summary of Section 4, the DFC technique utilizes dual feedback loop compensation. In Figure 5-3, we examined the AC stability of the outer feedback loop. Now, we can analyze the inner feedback loop, which is responsible for high-frequency compensation. This inner loop is crucial for determining overall AC loop stability, and can be simplified as the Loop-Gain of the DFC technique. Figure 5-3 shows the AC loop gain stability analysis, and the compensation approach is detailed in the Precision Lab Series: Op Amp.

Figure 5-4 Open-loop AC Analysis in DFC shows a Phase Margin of 58° at the UGBW

From the AC stability analysis in Figure 5-4, the unity gain bandwidth of the loop gain is measured at 5.46MHz with a phase margin of approximately 58°, indicating that the overall DFC loop is stable.