SBOS092B June   1998  β€“ January 2025 XTR106

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linearization
      2. 6.3.2 Reverse-Voltage Protection
      3. 6.3.3 Overvoltage Surge Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 External Transistor
      2. 7.1.2 Loop Power Supply
      3. 7.1.3 Bridge Balance
      4. 7.1.4 Underscale Current
      5. 7.1.5 Low-Impedance Bridges
      6. 7.1.6 Other Sensor Types
      7. 7.1.7 Radio Frequency Interference
      8. 7.1.8 Error Analysis
    2. 7.2 Typical Applications
    3. 7.3 Layout
    4. 7.4 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
    2. 8.2 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

Figure 4-1 D Package, 14-Pin SOIC, and N Package, 14-Pin PDIP (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
B (Base) 9 Output Base connection for external transistor
E (Emitter) 8 Input Emitter connection for external transistor
IO 7 Output Regulated 4mA to 20mA current loop output
IRET 6 Input Local ground return pin for VREG, VREF5, and VREF2.5
Lin Polarity 12 Input Linearity correction circuit polarity setting. Connect to IRET to correct for positive nonlinearity, or connect to VREG to correct for negative nonlinearity or if not using the linearity correction feature
RG 3, 4 β€” Input stage gain setting pins. The resistance RG between pins 3 and 4 sets the gain of the voltage-to-current transfer function
RLIN 11 β€” Linearity correction resistor pin. The resistance RLIN between pins 1 and 11 sets the corrective factor of the linearity correction circuit
V+ 10 Power Loop power supply
VIN– 2 Input Negative (inverting) differential voltage input
VIN+ 5 Input Positive (noninverting) differential voltage input
VREF5 14 Output 5V reference voltage output
VREF2.5 13 Output 2.5V reference voltage output
VREG 1 Output 5.1V regulator voltage output