SBVS257 March   2025 TPS7A56

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage Setting and Regulation
      2. 6.3.2 Low-Noise, Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 6.3.3 Programmable Soft-Start (NR/SS Pin)
      4. 6.3.4 Precision Enable and UVLO
      5. 6.3.5 Charge Pump Enable and BIAS Rail
      6. 6.3.6 Power-Good Pin (PG Pin)
      7. 6.3.7 Active Discharge
      8. 6.3.8 Thermal Shutdown Protection (TSD)
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
      4. 6.4.4 Current-Limit Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1  Precision Enable (External UVLO)
      2. 7.1.2  Undervoltage Lockout (UVLO) Operation
        1. 7.1.2.1 IN Pin UVLO
        2. 7.1.2.2 BIAS UVLO
        3. 7.1.2.3 Typical UVLO Operation
        4. 7.1.2.4 UVLO(IN) and UVLO(BIAS) Interaction
      3. 7.1.3  Dropout Voltage (VDO)
      4. 7.1.4  Input and Output Capacitor Requirements (CIN and COUT)
      5. 7.1.5  Recommended Capacitor Types
      6. 7.1.6  Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)
      7. 7.1.7  Optimizing Noise and PSRR
      8. 7.1.8  Adjustable Operation
      9. 7.1.9  Load Transient Response
      10. 7.1.10 Charge Pump Operation
      11. 7.1.11 Sequencing
      12. 7.1.12 Power-Good Functionality
      13. 7.1.13 Paralleling for Higher Output Current and Lower Noise
      14. 7.1.14 Power Dissipation (PD)
      15. 7.1.15 Estimating Junction Temperature
      16. 7.1.16 TPS7A57EVM-056 Thermal Analysis
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

7.1.6 Soft-Start, Noise Reduction (NR/SS Pin), and Power-Good (PG Pin)

The NR/SS pin has dual functionality. This pin controls the soft-start time and reduces the noise generated by the internal band-gap reference and the external resistor RREF. The NR/SS capacitor (CNR/SS) reduces the output noise to very low levels and sets the output ramp rate to limit inrush current.

The device features a programmable, monotonic, voltage-controlled, soft-start circuit that is set to work with an external capacitor (CNR/SS). In addition to the soft-start feature, the CNR/SS capacitor also lowers the output voltage noise of the LDO. Use the soft-start feature to eliminate power-up initialization problems. The controlled output voltage ramp also reduces peak inrush current during start up, minimizing start-up transients to the input power bus.

To achieve a monotonic start up, the device output voltage tracks the VNR/SS reference voltage until this reference reaches the set value (the set output voltage). The VNR/SS reference voltage is set by the RREF resistor. During start up, the device uses a fast charging current (IFAST_SS), as shown in Figure 7-4, to charge the CNR/SS capacitor.

Note: Any leakage on the NR/SS and REF pins directly impacts the accuracy of the reference voltage.
TPS7A56 Simplified Soft-Start CircuitFigure 7-4 Simplified Soft-Start Circuit

The 200μA (typical) INR/SS current quickly charges CNR/SS until the voltage reaches approximately 97% of the set output voltage. Then the ISS current turns off and the switch between REF and NR/SS closes. Thus leaving only the IREF current to charge CNR/SS to the set output voltage level.

Note: The discharge pulldown resistor on NR/SS (see the Functional Block Diagram) is engaged when any ground-referenced UVLOs are tripped, or when any faults occur. Such faults include overtemperature, POR, IREF bad, or OTP error faults. This resistor only engages when one of these events are active and the NRSS pin is above 50mV.

The soft-start ramp time depends on the fast start-up (INR/SS) charging current, the reference current (IREF), CNR/SS capacitor value, and the targeted output voltage (VOUT(target)). Equation 3 calculates the soft-start ramp time.

Equation 3. Soft-start time (tSS) = (VOUT(target) × CNR/SS) / ( ISS)

The ISS current is provided in the Typical Characteristics section and has a value of 200μA (typical). The IREF current has a value of 50μA (typical). The remaining 3% of the start-up time is determined by the RREF × CNR/SS time constant. Figure 7-5 shows the PG threshold at start-up.

TPS7A56 PG Threshold During Start-UpFigure 7-5 PG Threshold During Start-Up

The output voltage noise is lowered significantly by increasing the CNR/SS capacitor. The CNR/SS capacitor and RREF resistor form a LPF that filters out noise from the VREF voltage reference, thereby reducing the device noise floor. The low-pass filter (LPF) is a single-pole filter and Equation 4 calculates the LPF cutoff frequency. Increasing the CNR/SS capacitor significantly lowers output voltage noise, however, doing so lengthens start-up time. For low-noise applications, use a 4.7μF CNR/SS for optimal noise and start-up time trade off.

Equation 4. Cutoff Frequency (fcutoff) = 1 / (2 × π × RREF × CNR/SS)
Note: Current limit is entered during start up with a small CNR/SS and large COUT because VOUT no longer tracks the soft-start ramp.

Figure 7-6 shows the impact of the CNR/SS capacitor on the LDO output voltage noise.

TPS7A56 Output Voltage Noise Density vs CNR/SS With Charge Pump Enabled
CIN = 4.7μF, COUT = 22μF, VCP_EN = VEN, VIN = 5.3V,
VOUT = 5V, IOUT = 6A
Figure 7-6 Output Voltage Noise Density vs CNR/SS With Charge Pump Enabled